Abstract: Apparatus and method for compiling and executing hybrid classical-quantum programs. For example, one embodiment of an apparatus comprises: a host processor to perform a partial compilation on hybrid quantum-classical source code to generate one or more sequential blocks of quantum operations; a quantum compiler accelerator to receive compilation work offloaded by the host processor including the one or more sequential blocks of quantum operations, the quantum compiler to perform optimization operations to optimize runtime execution of one or more of the quantum operations in view if a quantum accelerator architecture to generate optimized quantum operations; and a quantum execution accelerator having the quantum accelerator architecture to execute the optimized quantum operations to manipulate a state of one or more qubits, to measure a state of the one or more qubits, and to provide measurement data indicating the state to the host processor.

Abstract: Technologies for the reduction of memory effects in a capacitor are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes an array of capacitors that can be charged to a voltage based on a voltage to be applied to a gate of the quantum processor. The capacitors in the array of capacitors are connected to the gate one at a time, charging up a parasitic capacitance. As more capacitors are switched, the voltage on the gate approaches a target voltage with an exponentially-decreasing voltage error.

Abstract: Technologies for a high-voltage transmission gate are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes one or more high-voltage transmission gates that can be used to charge capacitors linked to gates of qubits on the quantum processor. The transmission gate includes transistors with a breakdown voltage less than a range of input and output voltages of the transmission gate. Control circuitry on the companion chip controls the voltages applied to transistors of the transmission gate to ensure that the voltage differences across the terminals of each transistor is below a breakdown voltage.

Abstract: Technologies for a hybrid digital/analog processor for a quantum computer are disclosed. In the illustrative embodiment, a hybrid digital/analog processor may be able to process digital instructions as well as analog instructions. The digital instructions may be, e.g., read from or write to memory or registers, perform an arithmetic operation, perform a branch, etc. The analog instructions may be to, e.g., provide an analog voltage to a particular electrode of a qubit, provide an analog pulse to a qubit, measure a reflection of an analog signal from a qubit, etc. The integration of analog operations in the hybrid digital/analog processor can improve performance by, e.g., lowering latency and lowering power usage.

Abstract: Apparatus and methods for interfacing an integrated qubit control chip and a solid state qubit; detecting a qubit state with a transition pulse histogram; high resolution and high speed rectangular pulse generation; large-scale spin qubit state readout; and activity-based clock control.

Abstract: Technologies for high-speed interfaces for cryogenic quantum control are disclosed. In the illustrative embodiment, a die for quantum/classical interface circuitry includes digital circuitry operating in a first clock domain and analog circuitry operating in a second clock domain. Clock domain crossing circuitry facilitates asynchronous data transfer from the digital circuitry to the analog circuitry. The illustrative clock domain crossing circuitry includes a first asynchronous first-in-first-out (FIFO) queue at the border of the first clock domain. The first asynchronous FIFO queue is connected to a second asynchronous FIFO queue at the border of the second clock domain.

Abstract: Technologies for signal conditioning for signals for qubits are disclosed. In the illustrative embodiment, a finite impulse response filter is applied to a control signal for a target qubit to filter out a frequency corresponding to a collateral qubit. An infinite impulse response filter is then applied to the signal after the finite impulse response filter, which amplifies some of the frequencies filtered out by the finite impulse response, narrowing the bandwidth that is filtered out. Such an approach reduces the attenuation of the signal and can be used to reduce memory requirements of quantum/classical interface circuitry.