Abstract: A circuit for controlling a wordline in an SRAM includes an X address decoder for receiving and decoding a series of X addresses, and forwarding X addresses of a relevant cell, a cell block having a plurality of wordlines respectively connected to cells for storage of data, and a plurality of bitlines perpendicular to the wordlines, a wordline driver for receiving the X addresses, and forwarding a wordline enable signal for the cell block, a column selector for selecting one pair of bitlines from the plurality of bitlines, a sense amplifier for amplifying, and forwarding an output of the column selector in reading, a write driver for receiving, and providing a driving signal, and a wordline control part for selecting one of a write driver enable signal in writing and a sense amplifier enable signal in reading in response to a read/write identifying signal, to generate a control signal, and forward the control signal after delay of a preset time period, for disabling the wordline.