Patents by Inventor Toh Kok Wei

Toh Kok Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Combined semiconductor device packaging system
    Patent number: 11948924
    Abstract: A combined semiconductor device package includes a first semiconductor device package having a first semiconductor chip housed within a first enclosure, and a first substrate coupled to the first enclosure. The first substrate includes first solder balls and second solder balls, each in electrical communication with the first semiconductor chip. The first semiconductor device further includes conductive pads directly coupled to the first substrate. The conductive pads are in electrical communication with the first and second solder balls. The combined semiconductor device package further includes a second semiconductor device package having a second semiconductor chip housed within a second enclosure, and third solder balls in electrical communication with the second semiconductor chip, and coupled to the conductive pads of the first semiconductor device package.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: April 2, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Uthayarajan A L Rasalingam, Toh Kok Wei
  • COMBINED SEMICONDUCTOR DEVICE PACKAGING SYSTEM
    Publication number: 20220392877
    Abstract: A combined semiconductor device package includes a first semiconductor device package having a first semiconductor chip housed within a first enclosure, and a first substrate coupled to the first enclosure. The first substrate includes first solder balls and second solder balls, each in electrical communication with the first semiconductor chip. The first semiconductor device further includes conductive pads directly coupled to the first substrate. The conductive pads are in electrical communication with the first and second solder balls. The combined semiconductor device package further includes a second semiconductor device package having a second semiconductor chip housed within a second enclosure, and third solder balls in electrical communication with the second semiconductor chip, and coupled to the conductive pads of the first semiconductor device package.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 8, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Uthayarajan A/L Rasalingam, Toh Kok Wei