Patents by Inventor Tohru Fujita

Tohru Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240155769
    Abstract: A method for forming a functional layer includes giving information to the functional layer while forming the functional layer on a surface of an object. The functional layer includes an information area having the information and a non-information area other than the information area. The information area is different in color from the non-information area.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 9, 2024
    Applicant: Ricoh Company, Ltd.
    Inventors: Yukihiro WAKABAYASHI, Takashi FUJITA, Hiroyuki HIRATSUKA, Kohji TAKEUCHI, Tohru HASEGAWA, Hirotaka UNNO
  • Patent number: 7598138
    Abstract: Provided is a semiconductor device manufacturing method including the steps of: forming an n-type impurity diffusion region by ion-implanting arsenic into a capacitor formation region of a silicon substrate under a condition that a beam current is not less than 1 ?A but less than 3 mA; forming a capacitor dielectric film on the capacitor formation region of the silicon substrate; and forming a capacitor upper electrode on the capacitor dielectric film.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: October 6, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Tohru Fujita
  • Publication number: 20070048933
    Abstract: Provided is a semiconductor device manufacturing method including the steps of: forming an n-type impurity diffusion region by ion-implanting arsenic into a capacitor formation region of a silicon substrate under a condition that a beam current is not less than 1 ?A but less than 3 mA; forming a capacitor dielectric film on the capacitor formation region of the silicon substrate; and forming a capacitor upper electrode on the capacitor dielectric film.
    Type: Application
    Filed: December 23, 2005
    Publication date: March 1, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Tohru Fujita
  • Patent number: 7109128
    Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: September 19, 2006
    Assignee: Fujitsu Limited
    Inventors: Koichi Sugiyama, Yoshihiro Takao, Shinji Sugatani, Daisuke Matsunaga, Takayuki Wada, Tohru Fujita, Hikaru Kokura
  • Publication number: 20040224517
    Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.
    Type: Application
    Filed: June 15, 2004
    Publication date: November 11, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Koichi Sugiyama, Yoshihiro Takao, Shinji Sugatani, Daisuke Matsunaga, Takayuki Wada, Tohru Fujita, Hikaru Kokura
  • Patent number: 6800909
    Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: October 5, 2004
    Assignee: Fujitsu Limited
    Inventors: Koichi Sugiyama, Yoshihiro Takao, Shinji Sugatani, Daisuke Matsunaga, Takayuki Wada, Tohru Fujita, Hikaru Kokura
  • Publication number: 20030067045
    Abstract: There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an upper surface of the semiconductor substrate, first and second impurity diffusion regions of opposite conductivity type formed in the semiconductor substrate on both sides of the gate electrode and serving as source/drain, a channel region of one conductivity type formed below the gate electrode between the first and second impurity diffusion regions of opposite conductivity type, and pocket regions of one conductivity type connected to end portions of the impurity diffusion regions of opposite conductivity type in the semiconductor substrate below the gate electrode and having an impurity concentration of one conductivity type higher than the channel region.
    Type: Application
    Filed: October 2, 2002
    Publication date: April 10, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Koichi Sugiyama, Yoshihiro Takao, Shinji Sugatani, Daisuke Matsunaga, Takayuki Wada, Tohru Fujita, Hikaru Kokura