Patents by Inventor Tohru Fukuda

Tohru Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210269420
    Abstract: The present invention provides a heterocyclic compound having an orexin type 2 receptor agonist activity. A compound represented by the formula (I): wherein each symbol is as described in the specification, or a salt thereof has an orexin type 2 receptor agonist activity, and is useful as an agent for the prophylaxis or treatment of narcolepsy.
    Type: Application
    Filed: June 27, 2019
    Publication date: September 2, 2021
    Applicant: Takeda Pharmaceutical Company Limited
    Inventors: Tatsuhiko FUJIMOTO, Koichiro FUKUDA, Hiromichi SUGIMOTO, Kentaro RIKIMARU, Yoshihiro BANNO, Takahiro MATSUMOTO, Norihito TOKUNAGA, Yoshihide TOMATA, Yuji ISHICHI, Shogo MARUI, Tsuneo ODA, Tohru MIYAZAKI, Yasutaka HOASHI, Yasushi HATTORI, Yuichi KAJITA, Yuhei MIYANOHANA, Tatsuki KOIKE
  • Patent number: 11106106
    Abstract: An electrochromic device reversibly and controllably colored and decolored by electricity is provided. The electrochromic device is configured to control at least one of the following functions f1 and f2 based on at least one of an operating environment temperature of the electrochromic device, a continuous elapsed time of a colored state or a decolored state, and an illuminance around the electrochromic device: a function f1 of transiting to a colored state and/or limiting transition to a decolored state; and a function f2 of transiting to a decolored state and/or limiting transition to a colored state.
    Type: Grant
    Filed: March 17, 2019
    Date of Patent: August 31, 2021
    Assignee: RICOH COMPANY, LTD.
    Inventors: Noboru Sasa, Keiichiroh Yutani, Tohru Yashiro, Tomoo Fukuda, Masato Shinoda, Fuminari Kaneko
  • Patent number: 9891825
    Abstract: According to one embodiment, a memory system includes a first storage area and a controller. The first storage area configured to store therein data sent from a host. The size of the first storage area is a first size larger than a second size. The second size is a size of a logical address space which is assigned to a memory system by the host. The controller is configured to change the second size in response to a request from the host while at least a part of data in the logical address space stays valid.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: February 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Takahiro Nango, Yoshihisa Kojima, Tohru Fukuda
  • Patent number: 9798470
    Abstract: According to one embodiment, a memory system includes a non-volatile first memory, a second memory, and a memory controller. The memory controller is configured to store a plurality of translation information in the first memory and perform a first process in a case of starting. The translation information indicates a relation between a first address designated from the outside and a second address indicating a location in the first memory. The first process is a process in which the memory controller acquires the plurality of translation information from the first memory in an order of a storage location of the translation information in the first memory, and stores the plurality of acquired translation information in the second memory.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: October 24, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Tohru Fukuda, Shinichiro Nakazumi, Yoshihisa Kojima
  • Publication number: 20170176594
    Abstract: This obstacle detection device is mounted on a vehicle. This obstacle detection device includes a plurality of ultrasonic sensors, and a detector. The plurality of ultrasonic sensors transmits a plurality of ultrasonic waves of different frequencies to detection areas which overlap with each other at transmission timings which overlap with each other, and each of the ultrasonic sensors receives a returning ultrasonic wave. The detector identifies which one ultrasonic wave of a plurality of ultrasonic waves is reflected as the received returning ultrasonic wave, and detects a position of an obstacle existing around the vehicle.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Inventors: TORU ICHIKAWA, SHINYA OGAWA, TOHRU FUKUDA, YUKI OSATO
  • Publication number: 20160216887
    Abstract: According to one embodiment, a memory system includes a non-volatile first memory, a second memory, and a memory controller. The memory controller is configured to store a plurality of translation information in the first memory and perform a first process in a case of starting. The translation information indicates a relation between a first address designated from the outside and a second address indicating a location in the first memory. The first process is a process in which the memory controller acquires the plurality of translation information from the first memory in an order of a storage location of the translation information in the first memory, and stores the plurality of acquired translation information in the second memory.
    Type: Application
    Filed: September 10, 2015
    Publication date: July 28, 2016
    Inventors: Tohru Fukuda, Shinichiro Nakazumi, Yoshihisa Kojima
  • Publication number: 20160216894
    Abstract: According to one embodiment, a memory system includes a first storage area and a controller. The first storage area configured to store therein data sent from a host. The size of the first storage area is a first size larger than a second size. The second size is a size of a logical address space which is assigned to a memory system by the host. The controller is configured to change the second size in response to a request from the host while at least a part of data in the logical address space stays valid.
    Type: Application
    Filed: September 11, 2015
    Publication date: July 28, 2016
    Inventors: Takahiro Nango, Yoshihisa Kojima, Tohru Fukuda
  • Patent number: 9304952
    Abstract: According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: April 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takahiro Nango, Hiroyuki Moro, Tohru Fukuda
  • Patent number: 9252810
    Abstract: According to one embodiment, a controller writes first write data transferred from a first buffer and code data for second write data different from the first write data, the code data being transferred from a second buffer, in parallel to a plurality of physical pages corresponding to a first logical page. The controller writes code data for the first write data to a physical page corresponding to a second logical page, the second logical page being next to the first logical page, at a time of write to the nonvolatile memory following the write of the first write data and the code data for the second write data.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: February 2, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tohru Fukuda
  • Publication number: 20150236716
    Abstract: According to one embodiment, a controller writes first write data transferred from a first buffer and code data for second write data different from the first write data, the code data being transferred from a second buffer, in parallel to a plurality of physical pages corresponding to a first logical page. The controller writes code data for the first write data to a physical page corresponding to a second logical page, the second logical page being next to the first logical page, at a time of write to the nonvolatile memory following the write of the first write data and the code data for the second write data.
    Type: Application
    Filed: July 29, 2014
    Publication date: August 20, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Tohru FUKUDA
  • Patent number: 8914592
    Abstract: According to one embodiment, a data storage apparatus includes a write command module, a read command module, and a controller. The write command module is configured to process a write command for writing data to the nonvolatile memories for a plurality of channels, respectively. The read command module is configured to process a read command usually and to process a read command for read modify write (RMW) operation. The controller is configured to control the read command module, causing to execute the read command for the RMW operation, prior to the normal read command, thereby to execute a flush command, and to control the write command module, causing to execute a write flush process that includes the processing of a write command for the RMW operation after the read command for the RMW operation has been executed.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akinori Harasawa, Tohru Fukuda
  • Patent number: 8856468
    Abstract: According to one embodiment, a memory device includes a memory unit, a first storage unit, a second storage unit, a third storage unit, a data move unit, and a controller. The first storage unit stores a logical address and an intermediate address. The second storage unit stores the intermediate address and the physical address corresponding to the intermediate address. The third storage unit stores a flag corresponding to the logical address and the intermediate address. The flag represents whether read of latest data by a read operation has succeeded. When the flag stored in the third storage unit represents a success of the read of the latest data, the controller determines whether write has been done for the same logical address of the memory unit during the data move processing, and if the write has been done, invalidates the data move processing.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: October 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tohru Fukuda
  • Publication number: 20140013031
    Abstract: According to one embodiment, a data storage apparatus comprises a first controller, a second controller, a third controller, and a fourth controller. The first controller controls a flash memory, writing and reading data, in units of blocks, to and from the flash memory. The second controller detects any a write-interrupted block is interrupted by the first controller. The third controller sets the write-interrupted block detected by the second controller, as a block to be refreshed in another block. The fourth controller performs the process of refreshing.
    Type: Application
    Filed: November 27, 2012
    Publication date: January 9, 2014
    Inventors: Yoko MASUO, Gen Ohshima, Hironobu Miyamoto, Tohru Fukuda, Yoshimasa Aoyama
  • Patent number: 8568833
    Abstract: There is provided a process for formation of a multi-layered coating film, which includes sequentially coating a first colored coating composition, a second colored coating composition and a clear coating composition (C), and simultaneously heating and curing the obtained first colored coating film, second colored coating film and clear coating film to form a multi-layered coating film, where the first colored coating composition contains (a1) a polyester resin containing a hydroxyl group, which contains 1.0-8.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: October 29, 2013
    Assignee: Kansai Paint Co., Ltd.
    Inventors: Tohru Fukuda, Keisuke Sai, Remi Kasai
  • Patent number: 8359425
    Abstract: According to one embodiment, a memory control device includes a controller, a command queue module, a plurality of stage processors, and a skip module. The controller controls a data access command to a nonvolatile memory from a host. The command queue module queues a transfer request command corresponding to the data access command. The stage processors each perform stage processing related to the transfer request command queued by the command queue module. The skip module skips the stage processing by the stage processors in response to a shutdown command from the controller.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: January 22, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaka Iwasaki, Hirotaka Suzuki, Tohru Fukuda, Motohiro Matsuyama, Yoshimasa Aoyama
  • Publication number: 20120183796
    Abstract: There is provided a process for formation of a multi-layered coating film, which includes sequentially coating a first colored coating composition, a second colored coating composition and a clear coating composition (C), and simultaneously heating and curing the obtained first colored coating film, second colored coating film and clear coating film to form a multi-layered coating film, where the first colored coating composition contains (a1) a polyester resin containing a hydroxyl group, which contains 1.0-8.
    Type: Application
    Filed: September 27, 2010
    Publication date: July 19, 2012
    Inventors: Tohru Fukuda, Keisuke Sai, Remi Kasai
  • Publication number: 20120140561
    Abstract: According to one embodiment, a memory device includes a memory unit, a first storage unit, a second storage unit, a third storage unit, a data move unit, and a controller. The first storage unit stores a logical address and an intermediate address. The second storage unit stores the intermediate address and the physical address corresponding to the intermediate address. The third storage unit stores a flag corresponding to the logical address and the intermediate address. The flag represents whether read of latest data by a read operation has succeeded. When the flag stored in the third storage unit represents a success of the read of the latest data, the controller determines whether write has been done for the same logical address of the memory unit during the data move processing, and if the write has been done, invalidates the data move processing.
    Type: Application
    Filed: October 21, 2011
    Publication date: June 7, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tohru Fukuda
  • Publication number: 20120144094
    Abstract: According to one embodiment, a data storage apparatus includes a write command module, a read command module, and a controller. The write command module is configured to process a write command for writing data to the nonvolatile memories for a plurality of channels, respectively. The read command module is configured to process a read command usually and to process a read command for read modify write (RMW) operation. The controller is configured to control the read command module, causing to execute the read command for the RMW operation, prior to the normal read command, thereby to execute a flush command, and to control the write command module, causing to execute a write flush process that includes the processing of a write command for the RMW operation after the read command for the RMW operation has been executed.
    Type: Application
    Filed: November 17, 2011
    Publication date: June 7, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akinori Harasawa, Tohru Fukuda
  • Patent number: 8185687
    Abstract: According to one embodiment, a semiconductor storage device includes a queuing buffer, a read module, a separating module, a write command issuing module, and a write module. The write command issuing module is configured to add a write address indicated by write pointer information to the management data obtained by the separating module in order to issue a write command, and to automatically queue the write command into the queuing buffer. The write module is configured to supply the write command issued by the write command issuing module to the nonvolatile memory in order to write data into the nonvolatile memory.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: May 22, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Motohiro Matsuyama, Tohru Fukuda, Hiroyuki Moro
  • Publication number: 20120102262
    Abstract: According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.
    Type: Application
    Filed: August 8, 2011
    Publication date: April 26, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takahiro NANGO, Hiroyuki MORO, Tohru FUKUDA