Patents by Inventor Tohru Hara

Tohru Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955097
    Abstract: A shift register includes stages each constituted by a unit circuit provided with a thin-film transistor (separation transistor) that separates a control node into an output-side first control node and an input-side second control node and a capacitor whose first end is connected to the second control node. The thin-film transistor (separation transistor) has a control terminal that is supplied with a high-level DC power supply voltage. Typically, the channel width of a thin-film transistor (first output control transistor) that controls output from a unit circuit is ten or more times greater than the channel width of the thin-film transistor (separation transistor).
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: April 9, 2024
    Assignee: Sharp Display Technology Corporation
    Inventors: Jun Nishimura, Yoshihito Hara, Yohei Takeuchi, Kengo Hara, Tohru Daitoh
  • Publication number: 20240112646
    Abstract: A set circuit in a unit circuit in a gate driver of a display device includes a setting transistor, a first auxiliary transistor, and a second auxiliary transistor. The setting transistor includes a source terminal connected to an internal node, a gate terminal connected to a set input terminal, and a drain terminal connected to the set input terminal via the first auxiliary transistor and also connected to an input terminal via the second auxiliary transistor in a diode-connected form. Each transistor is controlled to be in an on state and an off state during normal drive and is controlled to be in the off state and the on state during a pause period by a control signal supplied to the input terminal.
    Type: Application
    Filed: August 14, 2023
    Publication date: April 4, 2024
    Inventors: Jun NISHIMURA, Kengo HARA, Yohei TAKEUCHI, Yoshihito HARA, Tohru DAITOH
  • Patent number: 11927860
    Abstract: An active matrix substrate includes a plurality of thin film transistors including an oxide semiconductor layer, an interlayer insulating layer, a plurality of pixel electrodes arranged above the interlayer insulating layer, a common electrode arranged between the pixel electrode and the interlayer insulating layer and also configured to function as a touch sensor electrode, a first dielectric layer arranged between the interlayer insulating layer and the common electrode, a second dielectric layer arranged between the common electrode and the pixel electrode, a plurality of touch wiring lines arranged between the interlayer insulating layer and the common electrode and formed of a third conductive film, and a plurality of pixel contact portions, in which each of the plurality of pixel contact portions includes a drain electrode of the thin film transistor, a connection electrode formed of the third conductive film and electrically connected to the drain electrode in a lower opening formed in the interlayer i
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 12, 2024
    Assignee: SHARP DISPLAY TECHNOLOGY CORPORATION
    Inventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Teruyuki Ueda, Masaki Maeda, Tatsuya Kawasaki, Yoshiharu Hirata
  • Patent number: 7295102
    Abstract: When an alarm switch of a transmitter is given a long press carried out for one or more seconds in a timer-reset condition, a first alarm reversal signal is transmitted simultaneously with the setting (starting) of the timer. If the alarm switch is pressed within the set time of the timer regardless of a press time period, a second alarm reversal signal is transmitted, and the timer is reset. On a receiver side, the activation and deactivation of the alarm is alternately performed upon receipt of each alarm reversal signal.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: November 13, 2007
    Assignee: Mitsubishi Jidosha Kogyo Kabushiki Kaisha
    Inventors: Toshihiko Yamazaki, Tohru Hara
  • Publication number: 20050253705
    Abstract: When an alarm switch of a transmitter is given a long press carried out for one or more seconds in a timer-reset condition, a first alarm reversal signal is transmitted simultaneously with the setting (starting) of the timer. If the alarm switch is pressed within the set time of the timer regardless of a press time period, a second alarm reversal signal is transmitted, and the timer is reset. On a receiver side, the activation and deactivation of the alarm is alternately performed upon receipt of each alarm reversal signal.
    Type: Application
    Filed: May 12, 2005
    Publication date: November 17, 2005
    Inventors: Toshihiko Yamazaki, Tohru Hara
  • Publication number: 20040211673
    Abstract: A plating solution containing 10 to 40 wt % of copper hexafluorosilicate. With the use of this plating solution, a copper thin film which has a low film stress and a low resistivity and which strongly (111)-oriented is plating-deposited on the fine pattern portion a copper seed layer, and film peeling caused by deterioration of an adhesion force between an underlying barrier layer and a copper seed layer even in a heat treatment process and in a chemical mechanical polishing (CMP) process after plating deposition is prevented.
    Type: Application
    Filed: May 21, 2004
    Publication date: October 28, 2004
    Applicants: Morita Chemical Industries Co., Ltd., Tohru Hara
    Inventors: Tohru Hara, Shoichi Ishida, Mitsuo Miyamoto, Tetsuo Yonezawa
  • Publication number: 20030111354
    Abstract: A plating solution containing 10 to 40 wt % of copper hexafluorosilicate. With the use of this plating solution, a copper thin film which has a low film stress and a low resistivity and which strongly (111)-oriented is plating-deposited on the fine pattern portion a copper seed layer, and film peeling caused by deterioration of an adhesion force between an underlying barrier layer and a copper seed layer even in a heat treatment process and in a chemical mechanical polishing (CMP) process after plating deposition is prevented.
    Type: Application
    Filed: April 9, 2002
    Publication date: June 19, 2003
    Inventors: Tohru Hara, Shoichi Ishida, Mitsuo Miyamoto, Tetsuo Yonezawa
  • Patent number: 6246082
    Abstract: There is provided a semiconductor memory device with extremely less deterioration of characteristics of dielectric thin film and with high stability. A TaSiN barrier metal layer 13 is formed on a Pt upper electrode 12. This TaSiN barrier metal layer 13 has electrical conductivity and hydrogen-gas blocking property and besides has an amorphous structure stable in high temperature region without crystallizing even during firing for crystallization of an oxide ferroelectric thin film (SBT thin film) 11. Then, hydrogen gas generated during later formation of a second interlayer insulating film 15 is reliably blocked from invading into the oxide ferroelectric thin film 11, by which characteristic deterioration of the oxide ferroelectric thin film 11 due to hydrogen gas is prevented.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: June 12, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shun Mitarai, Shigeo Ohnishi, Tohru Hara
  • Patent number: 4088514
    Abstract: Thin epitaxial layers of Group III-V semiconductor materials are grown from solution with improved thickness reproducibility and surface smoothness by a method including the steps of preparing an ideally saturated solution of the semiconductor material in a metal melt preferably by keeping an undersaturated solution in contact with the crystalline semiconductor material at a predetermined temperature, supercooling the saturated solution and then bringing the supercooled solution into contact with a substrate. A growth boat assembly for this method has at least one set of two boats slidably stacked one upon another, wherein the upper boat has a solution reservoir and the lower boat has two depressions respectively for receiving therein the substrate and the crystalline semiconductor material as the source material at the saturation step, arranged such that a solution contained in the reservoir can selectively be contacted with either of the source material and the substrate and isolated from both.
    Type: Grant
    Filed: April 9, 1976
    Date of Patent: May 9, 1978
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tohru Hara, Minoru Mihara, Nobuyuki Toyoda