Abstract: There is provided a semiconductor device including a wafer and a focus monitoring pattern formed on the wafer. The focus monitoring pattern has at least one pair of first and second patterns. The first pattern has an unexposed region surrounded by an exposed region and the second pattern has an exposed region surrounded by an unexposed region. In addition, the present invention provides a method of fabricating a semiconductor device comprising the steps of forming at least one pair of first and second patterns on a wafer. The first pattern has an unexposed region surrounded by an exposed region and the second pattern has an exposed region surrounded by an unexposed region. The method further comprises checking a focusing condition on exposure by measuring widths of the first and second patterns formed on the wafer.

Abstract: There is provided a semiconductor device including a wafer and a focus monitoring pattern formed on the wafer. The focus monitoring pattern having at least one pair of first and second patterns, and the first pattern has an unexposed region surrounded by an exposed region, and the second pattern has an exposed region surrounded by an unexposed region. In addition, the present invention provides a method of fabricating a semiconductor device comprising the steps of forming at least one pair of first and second patterns on a wafer, the first pattern having an unexposed region surrounded by an exposed region, the second pattern having an exposed region surrounded by an unexposed region, and checking a focusing condition on exposure by measuring widths of the first and second patterns formed on the wafer.

Abstract: Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.

Abstract: There is provided a semiconductor device including a wafer and a focus monitoring pattern formed on the wafer. The focus monitoring pattern having at least one pair of first and second patterns, and the first pattern has an unexposed region surrounded by an exposed region, and the second pattern has an exposed region surrounded by an unexposed region. In addition, the present invention provides a method of fabricating a semiconductor device comprising the steps of forming at least one pair of first and second patterns on a wafer, the first pattern having an unexposed region surrounded by an exposed region, the second pattern having an exposed region surrounded by an unexposed region, and checking a focusing condition on exposure by measuring widths of the first and second patterns formed on the wafer.

Abstract: Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.

Abstract: Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.

Abstract: Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.

Abstract: A monolithic type varistor in which a plurality of inner electrodes are arranged in a sintered body composed of semiconductor ceramics so as to be overlapped with each other while being separated by semiconductor ceramic layers. The plurality of inner electrodes are electrically connected to first and second outer electrodes formed on both end surfaces of the sintered body. One or more non-connected type inner electrodes are arranged between adjacent ones of the plurality of inner electrodes and are not electrically connected to the outer electrodes, each of the non-connected type inner electrodes being spaced apart from each adjacent inner electrode or non-connected type inner electrode while being separated therefrom by a semiconductor ceramic layer. Voltage non-linearity is obtained by Schottky barriers formed at the interface of the inner electrode and the semiconductor ceramic layer and the interface of the non-connected type inner electrode and the semiconductor ceramic layer.