Patents by Inventor Tohru Ichikawa

Tohru Ichikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11997889
    Abstract: Frame wiring lines are provided in a frame region, a flattening film in which a frame-shaped slit is formed in the frame region is provided in the display region and the frame region, a plurality of first electrodes constituting light-emitting elements are provided on the flattening film, and conductive layer made of the same material and formed in the same layer as those of each of the plurality of first electrodes are provided covering at least end faces of the frame wiring lines exposed from the slit.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 28, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroki Taniyama, Ryosuke Gunji, Shinsuke Saida, Shinji Ichikawa, Tohru Okabe, Kohji Ariga, Akira Inoue, Yoshihiro Kohara, Koji Tanimura, Yoshihiro Nakada, Hiroharu Jinmura
  • Publication number: 20240164151
    Abstract: Provided is the following: a resin substrate layer; a thin-film transistor layer provided on the resin substrate layer, and having a stack of, in sequence, a gate insulating film, an interlayer insulating film, and a flattening film; and a light-emitting element layer provided on the thin-film transistor layer, with a plurality of first electrodes, a common edge cover that is common, a plurality of light-emitting function layers, and a second electrode that is common being stacked sequentially in correspondence with a plurality of subpixels constituting a display region. A non-display region that is in the form of an island within the display region has a through-hole. The non-display region includes a first light-blocking film provided on the periphery of the flattening film so as to cover the side wall of the periphery.
    Type: Application
    Filed: March 31, 2021
    Publication date: May 16, 2024
    Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
  • Publication number: 20240147789
    Abstract: A display device, includes: a base substrate layer; a thin-film transistor layer provided on the base substrate layer, and including a plurality of subpixels forming a display region, each of the subpixels being provided with a thin-film transistor on which a planarization film is stacked; and a light-emitting element layer provided on the thin-film transistor layer, and including a plurality of first electrodes, a common edge cover, a plurality of light-emitting functional layers, and a common second electrode, all of which are sequentially stacked on top of another in association with the plurality of subpixels, wherein each of the first electrodes has a peripheral edge portion provided to: surround, in plan view, the thin-film transistor corresponding to the first electrode; and protrude toward the base substrate layer.
    Type: Application
    Filed: April 27, 2021
    Publication date: May 2, 2024
    Inventors: Tohru OKABE, Shoji OKAZAKI, Shinsuke SAIDA, Shinji ICHIKAWA, Hiroki TANIYAMA, Eiji FUJIMOTO
  • Patent number: 11968861
    Abstract: An organic EL display (1) has a bend (B) where a slit (81) is bored in a base coat film (23), gate insulating film (27), first interlayer insulating film (31) and second interlayer insulating film (35). The bend is provided with a filler layer (83) filling the slit and covering both edges of the slit. The filler layer has a protrusion (85) overlapping each edge in the width direction of the slit. A routed wire (7) routed from the display region (D) and then routed over the filler layer to reach a terminal section (T) extends over the protrusion.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: April 23, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Ichikawa, Shinsuke Saida, Ryosuke Gunji, Hiroki Taniyama, Tohru Okabe, Akira Inoue, Hiroharu Jinmura, Yoshihiro Nakada, Koji Tanimura
  • Patent number: 11957014
    Abstract: A display device includes: a plurality of control lines; a plurality of power supply lines; a plurality of data signal lines; an oxide semiconductor layer; a first metal layer; a gate insulation film; a first inorganic insulation film; a second metal layer; a second inorganic insulation film; and a third metal layer. The oxide semiconductor layer, in a plan view, contains therein semiconductor lines formed as isolated regions between a plurality of drivers and a display area. The semiconductor lines cross the plurality of control lines and the plurality of power supply lines, are in contact with the plurality of control lines via an opening in a gate insulation film, are in contact with the plurality of power supply lines via an opening in the first inorganic insulation film, and have a plurality of narrowed portions, such that thicker and thinner regions exist along the same line.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 9, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Hiroki Taniyama, Ryosuke Gunji, Kohji Ariga, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Hiroharu Jinmura, Akira Inoue
  • Patent number: 11950462
    Abstract: A first conductive layer in the same layer as that of a first electrode is coupled to a third conductive layer and a second electrode in the same layer as that of a third metal layer through a slit formed in a flattening film of a non-display area. Second conductive layers in the same layer as that of a second metal layer are provided to overlap with the slit.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 2, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Hiroki Taniyama, Ryosuke Gunji, Kohji Ariga, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Akira Inoue, Hiroharu Jinmura, Takeshi Yaneda
  • Patent number: 11931936
    Abstract: In an injection process, molten resin is successively injected from a first flow channel and a second flow channel connected with each other in order into a cavity of a metal mold. High-temperature resin existing in the first flow channel is injected in advance into the cavity as a part of a single shot of molten resin to later form a skin layer of a molded article. Other low temperature resin near a flowable limit existing in the second flow channel is subsequently injected into the cavity as another part of the single shot of molten resin to later form a core layer of the molded article. A low temperature resin remaining in the first flow channel when injection is completed is warmed to be a high-temperature resin before the next cycle, thereby allowing successive molding of molded articles.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: March 19, 2024
    Assignee: DENSO CORPORATION
    Inventors: Tohru Higuchi, Masato Ichikawa, Tsuyoshi Arai, Jun Hasebe, Atsushi Kawamura, Tomoyoshi Murata
  • Patent number: D277859
    Type: Grant
    Filed: March 29, 1983
    Date of Patent: March 5, 1985
    Assignee: Sony Corporation
    Inventors: Etsuro Saito, Tohru Ichikawa
  • Patent number: D284665
    Type: Grant
    Filed: October 24, 1983
    Date of Patent: July 15, 1986
    Assignee: Sony Corporation
    Inventors: Etsuro Saito, Tsuneo Nemoto, Tohru Ichikawa, Shinichiro Takahashi
  • Patent number: D314762
    Type: Grant
    Filed: October 3, 1988
    Date of Patent: February 19, 1991
    Assignee: Sony Corporation
    Inventors: Masayoshi Tsuchiya, Tohru Ichikawa