Patents by Inventor Tohru Ishizuka

Tohru Ishizuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9142449
    Abstract: The present invention is a method for manufacturing a bonded wafer, including performing a plasma activation treatment on at least one of the bonded surfaces of the bond wafer and the base wafer before bonding, wherein the plasma activation treatment is performed while a back surface of at least one of the bond wafer and the base wafer is placed on a stage with the back surface being in point contact or line contact with the stage. The method can inhibit increase in attached substances such as particles on the back surface of a wafer during the plasma activation treatment, and prevent re-attachment of the attached substances to the bonded surface of the wafer, particularly when the wafer after the plasma activation treatment is cleaned with a batch cleaning apparatus.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: September 22, 2015
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Tohru Ishizuka
  • Publication number: 20150118825
    Abstract: The present invention is a method for manufacturing a bonded wafer, including performing a plasma activation treatment on at least one of the bonded surfaces of the bond wafer and the base wafer before bonding, wherein the plasma activation treatment is performed while a back surface of at least one of the bond wafer and the base wafer is placed on a stage with the back surface being in point contact or line contact with the stage. The method can inhibit increase in attached substances such as particles on the back surface of a wafer during the plasma activation treatment, and prevent re-attachment of the attached substances to the bonded surface of the wafer, particularly when the wafer after the plasma activation treatment is cleaned with a batch cleaning apparatus.
    Type: Application
    Filed: April 2, 2013
    Publication date: April 30, 2015
    Applicant: Shin-Etsu Handotai Co., Ltd.
    Inventor: Tohru Ishizuka
  • Patent number: 8823130
    Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 2, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Kato, Satoshi Oka, Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Patent number: 8697544
    Abstract: The present invention is a method for manufacturing a bonded wafer including at least the steps of: forming an ion-implanted layer inside a bond wafer; bringing the ion-implanted surface of the bond wafer into close contact with a surface of a base wafer directly or through a silicon oxide film; and performing heat treatment for delaminating the bond wafer at the ion-implanted layer, wherein the heat treatment step for delaminating includes performing a pre-annealing at a temperature of less than 500° C. and thereafter performing a delamination heat treatment at a temperature of 500° C. or more, and the pre-annealing is performed at least by a heat treatment at a first temperature and a subsequent heat treatment at a second temperature higher than the first temperature.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: April 15, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tohru Ishizuka, Norihiro Kobayashi, Nobuhiko Noto
  • Patent number: 8466538
    Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: June 18, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tohru Ishizuka, Nobuhiko Noto, Norihiro Kobayashi, Masatake Nakano
  • Publication number: 20120326268
    Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.
    Type: Application
    Filed: March 1, 2011
    Publication date: December 27, 2012
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Masahiro Kato, Satoshi Oka, Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Patent number: 8338277
    Abstract: The present invention provides a method for manufacturing an SOI substrate including at least: an oxygen ion implantation step of ion-implanting oxygen ions from one main surface of a single-crystal silicon substrate to form an oxygen ion implanted layer; and a heat treatment step of performing a heat treatment with respect to the single-crystal silicon substrate having the oxygen ion implanted layer formed therein to change the oxygen ion implanted layer into a buried oxide film layer, wherein acceleration energy for the oxygen ion implantation is previously determined from a thickness of the buried oxide film layer to be obtained, and the oxygen ion implantation step is carried out with the determined acceleration energy to manufacture the SOI substrate. Thereby, it is possible to provide an SOI substrate manufacturing method that enables efficiently manufacturing an SOI substrate having a continuous and uniform thin buried oxide film layer.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: December 25, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroshi Takeno, Tohru Ishizuka, Nobuhiko Noto
  • Patent number: 8202787
    Abstract: A method for manufacturing an SOI wafer having a buried oxide film with a predetermined thickness including performing a heat treatment for reducing a thickness of the buried oxide film on an SOI wafer material having an SOI layer formed on the buried oxide film, wherein a thickness of the SOI layer of the SOI wafer material to be subjected to the heat treatment for reducing the thickness of the buried oxide film is calculated on the basis of a ratio of the thickness of the buried oxide film to be reduced by the heat treatment with respect to a permissible value of an amount of change in an in-plane range of the buried oxide film, the change being caused by the heat treatment, and the SOI wafer material obtained by thinning the thickness of the bond wafer so as to have the calculated thickness of the SOI layer is subjected to the heat treatment for reducing the thickness of the buried oxide film.
    Type: Grant
    Filed: November 11, 2009
    Date of Patent: June 19, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tohru Ishizuka, Norihiro Kobayashi, Hiroji Aga, Nobuhiko Noto
  • Patent number: 8097523
    Abstract: A method for manufacturing a bonded wafer, including at least implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer to form an ion-implanted layer in the wafer, bonding an ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an insulator film, and then delaminating the bond wafer at the ion-implanted layer to fabricate a bonded wafer. A plasma treatment is applied to a bonding surface of one of the bond wafer and the base wafer to grow an oxide film, etching the grown oxide film is carried out, and bonding to the other wafer is performed. The method enables preventing defects by reducing particles on the bonding surface and performing strong bonding when effecting bonding directly or through the insulator film.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: January 17, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Tohru Ishizuka, Hiroji Aga, Nobuhiko Noto
  • Publication number: 20110223740
    Abstract: A method for manufacturing an SOI wafer having a buried oxide film with a predetermined thickness including performing a heat treatment for reducing a thickness of the buried oxide film on an SOI wafer material having an SOI layer formed on the buried oxide film, wherein a thickness of the SOI layer of the SOI wafer material to be subjected to the heat treatment for reducing the thickness of the buried oxide film is calculated on the basis of a ratio of the thickness of the buried oxide film to be reduced by the heat treatment with respect to a permissible value of an amount of change in an in-plane range of the buried oxide film, the change being caused by the heat treatment, and the SOI wafer material obtained by thinning the thickness of the bond wafer so as to have the calculated thickness of the SOI layer is subjected to the heat treatment for reducing the thickness of the buried oxide film.
    Type: Application
    Filed: November 11, 2009
    Publication date: September 15, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tohru Ishizuka, Norihiro Kobayashi, Hiroji Aga, Nobuhiko Noto
  • Publication number: 20110212598
    Abstract: The present invention is a method for manufacturing a bonded wafer including at least the steps of: forming an ion-implanted layer inside a bond wafer; bringing the ion-implanted surface of the bond wafer into close contact with a surface of a base wafer directly or through a silicon oxide film; and performing heat treatment for delaminating the bond wafer at the ion-implanted layer, wherein the heat treatment step for delaminating includes performing a pre-annealing at a temperature of less than 500° C. and thereafter performing a delamination heat treatment at a temperature of 500° C. or more, and the pre-annealing is performed at least by a heat treatment at a first temperature and a subsequent heat treatment at a second temperature higher than the first temperature.
    Type: Application
    Filed: October 14, 2009
    Publication date: September 1, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tohru Ishizuka, Norihiro Kobayashi, Nobuhiko Noto
  • Publication number: 20110151643
    Abstract: A method for manufacturing a bonded wafer by forming an ion implanted layer in a bond wafer; bonding an ion implanted surface of the bond wafer to a surface of a base wafer directly or through a silicon oxide film; and performing a delamination heat treatment. After the formation of the ion implanted layer and before the bonding, a plasma treatment is carried out with respect to a bonding surface of at least one of the bond wafer and the base wafer. The delamination heat treatment is carried out at a fixed temperature by directly putting the bonded wafer into a heat-treating furnace whose furnace temperature is set to the fixed temperature less than 475° C. without a temperature increasing step.
    Type: Application
    Filed: August 4, 2009
    Publication date: June 23, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Hiroji Aga, Tohru Ishizuka
  • Publication number: 20110104870
    Abstract: A method for manufacturing a bonded wafer, including at least implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer to form an ion-implanted layer in the wafer, bonding an ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an insulator film, and then delaminating the bond wafer at the ion-implanted layer to fabricate a bonded wafer. A plasma treatment is applied to a bonding surface of one of the bond wafer and the base wafer to grow an oxide film, etching the grown oxide film is carried out, and bonding to the other wafer is performed. The method enables preventing defects by reducing particles on the bonding surface and performing strong bonding when effecting bonding directly or through the insulator film.
    Type: Application
    Filed: February 17, 2009
    Publication date: May 5, 2011
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Tohru Ishizuka, Hiroji Aga, Nobuhiko Noto
  • Patent number: 7861421
    Abstract: The present invention provides a method for measuring a rotation angle of a bonded wafer, wherein a base wafer and a bond wafer each having a notch indicative of a crystal orientation formed at an outer edge thereof are bonded to each other at a desired rotation angle by utilizing the notches, a profile of the bond wafer having a reduced film thickness is observed with respect to a bonded wafer manufactured by reducing a film thickness of the bond wafer, a positional direction of the notch of the bond wafer seen from a center of the bonded wafer is calculated by utilizing the profile, an angle formed between the calculated positional direction of the notch of the bond wafer and a positional direction of the notch of the base wafer is calculated, and a rotation angle of the base wafer and the bond wafer is measured.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: January 4, 2011
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Publication number: 20100323502
    Abstract: The present invention provides a method for manufacturing an SOI substrate including at least: an oxygen ion implantation step of ion-implanting oxygen ions from one main surface of a single-crystal silicon substrate to form an oxygen ion implanted layer; and a heat treatment step of performing a heat treatment with respect to the single-crystal silicon substrate having the oxygen ion implanted layer formed therein to change the oxygen ion implanted layer into a buried oxide film layer, wherein acceleration energy for the oxygen ion implantation is previously determined from a thickness of the buried oxide film layer to be obtained, and the oxygen ion implantation step is carried out with the determined acceleration energy to manufacture the SOI substrate. Thereby, it is possible to provide an SOI substrate manufacturing method that enables efficiently manufacturing an SOI substrate having a continuous and uniform thin buried oxide film layer.
    Type: Application
    Filed: February 19, 2008
    Publication date: December 23, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Takeno, Tohru Ishizuka, Nobuhiko Noto
  • Publication number: 20100314722
    Abstract: The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 ?·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.
    Type: Application
    Filed: February 19, 2009
    Publication date: December 16, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tohru Ishizuka, Nobuhiko Noto, Norihiro Kobayashi, Masatake Nakano
  • Patent number: 7799660
    Abstract: The present invention provides a method for manufacturing an SOI substrate by which an oxygen ion is implanted from at least one of main surfaces of a single-crystal silicon substrate to form an oxygen-ion-implanted layer and then an oxide film-forming heat treatment that changes the formed oxygen-ion-implanted layer into a buried oxide film layer is performed with respect to the single-crystal silicon substrate to manufacture the SOI substrate, the method comprising: implanting a neutral element ion having a dose amount of 1×1012 atoms/cm2 or above and less than 1×1015 atoms/cm2 into a back surface to form an ion-implanted damage layer after performing the oxide film-forming heat treatment; and gettering a metal impurity in the ion-implanted damage layer by a subsequent heat treatment to enable reducing a metal impurity concentration on a front surface side.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: September 21, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tohru Ishizuka, Hiroshi Takeno, Nobuhiko Noto
  • Publication number: 20100132205
    Abstract: The present invention provides a method for measuring a rotation angle of a bonded wafer, wherein a base wafer and a bond wafer each having a notch indicative of a crystal orientation formed at an outer edge thereof are bonded to each other at a desired rotation angle by utilizing the notches, a profile of the bond wafer having a reduced film thickness is observed with respect to a bonded wafer manufactured by reducing a film thickness of the bond wafer, a positional direction of the notch of the bond wafer seen from a center of the bonded wafer is calculated by utilizing the profile, an angle formed between the calculated positional direction of the notch of the bond wafer and a positional direction of the notch of the base wafer is calculated, and a rotation angle of the base wafer and the bond wafer is measured.
    Type: Application
    Filed: July 3, 2008
    Publication date: June 3, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Publication number: 20080261411
    Abstract: The present invention provides a method for manufacturing an SOI substrate by which an oxygen ion is implanted from at least one of main surfaces of a single-crystal silicon substrate to form an oxygen-ion-implanted layer and then an oxide film-forming heat treatment that changes the formed oxygen-ion-implanted layer into a buried oxide film layer is performed with respect to the single-crystal silicon substrate to manufacture the SOI substrate, the method comprising: implanting a neutral element ion having a dose amount of 1×1012 atoms/cm2 or above and less than 1×1015 atoms/cm2 into a back surface to form an ion-implanted damage layer after performing the oxide film-forming heat treatment; and gettering a metal impurity in the ion-implanted damage layer by a subsequent heat treatment to enable reducing a metal impurity concentration on a front surface side.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 23, 2008
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tohru Ishizuka, Hiroshi Takeno, Nobuhiko Noto
  • Patent number: 6423285
    Abstract: In a method for producing a silicon single crystal by growing a single crystal ingot while a magnetic field perpendicular to a crystal growth axis is applied to a silicon melt contained in a quartz crucible during pulling of the single crystal from the melt contained in the quartz crucible, the crystal growth is performed so that one of a low temperature region and a high temperature region generated at a surface of the silicon melt contained in the crucible should always cover a solid-liquid interface of the crystal growth, or a ratio of vertical magnetic field component to horizontal magnetic field component for magnetic field strength at the crystal center of the surface of the silicon melt contained in the quartz crucible is controlled to be 0.3 or more and 0.5 or less.
    Type: Grant
    Filed: November 7, 2000
    Date of Patent: July 23, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Kirio Itoi, Eiichi Iino, Tohru Ishizuka, Tomohiko Ohta, Izumi Fusegawa