Abstract: A controller executes an equalization process of equalizing capacities of a plurality of cells, and a cell abnormality determination process of, of detected voltages of the plurality of cells, calculating a voltage difference between a representative voltage based on the detected voltage of at least one cell to be compared and the detected voltage of one cell to be detected at a first time and a second time, and when a difference between the two voltage differences is greater than or equal to a threshold value, determining that the cell to be detected is abnormal. In the case of executing the cell abnormality determination process during the equalization process, the controller provides the detected voltage of a target cell to be subjected to the equalization process with a compensation value corresponding to a voltage change based on energy transfer in the target cell due to the equalization process between the first time and the second time, and calculates the voltage difference at the second time.

Abstract: Provided is a controller configured: to calculate, among voltages detected from a plurality of cells, a voltage difference between the voltage detected from one cell of the plurality of cells, the one cell to be detected, and a representative voltage at each of a first time and a second time, the representative voltage based on the voltage detected from at least one cell of the plurality of cells, the at least one cell to be compared; and when a discrepancy between the voltage difference at the first time and the voltage difference at the second time is equal to or more than a threshold, to determine that an abnormality has occurred in the one cell to be detected.

Abstract: A semiconductor memory device including at least one pair of memory cell arrays having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. A plurality of word line driving transistors are connected to the word lines and aligned at inner edges of the pair of memory cell arrays. The pitch of a pair of word line driving gate circuits is matched to the pitch of the two adjacent word line, and at least a pair of word lines driving gate circuits are arranged along the direction of the word lines between the pair of memory cell arrays. The outputs of the word line driving gate circuits are connected to the word line driving transistors. A plurality of decoder lines extend between the pair of word line driving gate circuits and are connected to the input terminals of the word line driving gate circuits.