Abstract: A semiconductor memory device including at least one pair of memory cell arrays having a plurality of word lines, a plurality of bit lines, and a plurality of memory cells disposed at intersections of the word lines and the bit lines. A plurality of word line driving transistors are connected to the word lines and aligned at inner edges of the pair of memory cell arrays. The pitch of a pair of word line driving gate circuits is matched to the pitch of the two adjacent word line, and at least a pair of word lines driving gate circuits are arranged along the direction of the word lines between the pair of memory cell arrays. The outputs of the word line driving gate circuits are connected to the word line driving transistors. A plurality of decoder lines extend between the pair of word line driving gate circuits and are connected to the input terminals of the word line driving gate circuits.