Abstract: The ferroelectric memory device includes (A) at least one memory cell array, the memory cell array including (a) a plurality of memory cells arranged in row and column directions, each of the memory cells having a capacitive element and a transistor, the capacitive element having a ferroelectric film interposed between electrodes facing to each other, storing and retaining binary data in accordance with polarization of the ferroelectric film, one of a source and a drain of the transistor being electrically connected to one of the electrodes of the capacitive element, and (b) a plate line being electrically connected to the other of the electrodes of the capacitive element; and (B) an arrangement for arranging a voltage of the plate line to be fixed and activating the transistor so as to arrange a voltage at a junction of the transistor and the capacitive element to be the same as the voltage of the plate line.

Abstract: A non-volatile ferroelectric memory device includes a plurality of memory cells provided in a matrix manner, each of which comprises a transistor having a gate and source and drain regions formed in a semiconductor region, and a ferroelectric capacitor having first and second electrodes and a ferroelectric layer interposed between the first and second electrodes. The second electrode is connected to one of the source and drain regions of the transistor.

Abstract: In a ferroelectric memory, when data is read out from a memory cell, a variation absorbing circuit minimizes a variation of the voltage on the pair of data signal lines caused by factor other than the current caused due to the polarization of the ferroelectric capacitor. Thus, a voltage not smaller than the coercive voltage can be applied between the opposing electrodes of the ferroelectric capacitor, with the result that a sufficient read-out signal voltage can be obtained.

Abstract: A BiMIS circuit includes a load pull-up bipolar transistor, a load pull-down bipolar transistor, a first MISFET and first and second MISFETs for driving the load pull-up bipolar transistor, and a third MISFET and a second MISFET for driving the load pull-down bipolar transistor. The second MISFET has a turn-on voltage lower than the turn-on voltage of the load pull-up bipolar transistor, and the second MISFET has a turn-on voltage lower than the turn-on voltage of the load pull-down bipolar transistor.

Abstract: A buffer circuit includes first and second differential amplification type buffer circuits. The input nodes of the first and second differential amplification type buffer circuits are connected together and the output nodes of the first and second differential amplification type buffer circuits are also connected to each other. The first differential amplification type buffer circuit is constituted by a pair of driving P-channel MOS transistors and N-channel MOS transistors acting as loads of the P-channel MOS transistors and connected to constitute a current mirror circuit. The second differential amplification type buffer circuit is constituted by P-channel MOS transistors acting as loads and connected to constitute a current mirror circuit and a pair of driving N-channel MOS transistors.

Abstract: A defect detection circuit for detecting a defect of a memory cell, a counter for counting defects detected by the defect detect circuit, and a remediableness determination unit for determining whether a count of the counter allows remedy by a redundancy circuit, are provided in a tester for a semiconductor memory or on a memory chip having a redundancy circuit. When the count of the counter is the same as or smaller than the number of at least one of the auxiliary rows and columns of the redundancy circuit, the memory is determined to be "remediable." Otherwise, the memory is determined to be "unremediable." When the count of the counter exceeds the number of at least one of the auxiliary rows and columns of the redundancy circuit, the memory test is interrupted.

Abstract: Improved method for producing anode aluminum foils for electrolytic condensers used in low and intermediate voltage applications in which a hard tempered aluminum foil consisting of 99.9 to 99.99% pure aluminum added with 0.010 to 0.25% by weight of copper is electrolytically etched in an aqueous solution of neutral chlorides such as sodium chloride, aluminum chloride or potassium chloride.

Abstract: A process for producing solar collectors of aluminum or aluminum alloys having a selective absorptive coating. Aluminum or its alloy is dipped in a hot aqueous solution containing a silicate. Aluminum alloys can be also used which contain alloying elements such as iron, copper, titanium, nickel, silver and gold.

Abstract: Aluminum foil for an electrode of an electrolytic capacitor is disclosed. The foil comprises at least one core layer adapted to prevent the growth of pits by electrolytic etching, and outer layers formed on both surfaces of the core layer. A large number of etching pits are produced in the outer layers. In a modification, the core layer contains more iron than the outer layers. Again in a modification, the core layer is covered or contained with aluminum oxides or hydroxides.