Patents by Inventor Tohru Kohda
Tohru Kohda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11108615Abstract: In accordance with an embodiment of the present invention, a method for receiving a signal, comprising the estimation step for estimating time and frequency shifts that are embedded in the received signal, to cancel-out shifts, wherein the method refers to the non-commutative shift parameter space of co-dimension 2.Type: GrantFiled: February 27, 2020Date of Patent: August 31, 2021Assignee: RADIUS CO., LTD.Inventor: Tohru Kohda
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Publication number: 20200204426Abstract: In accordance with an embodiment of the present invention, a method for receiving a signal, comprising the estimation step for estimating time and frequency shifts that are embedded in the received signal, to cancel-out shifts, wherein the method refers to the non-commutative shift parameter space of co-dimension 2.Type: ApplicationFiled: February 27, 2020Publication date: June 25, 2020Inventor: Tohru KOHDA
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Patent number: 10666486Abstract: In accordance with an embodiment of the present invention, a method for receiving a signal, comprising the estimation step for estimating time and frequency shifts that are embedded in the received signal, to cancel-out shifts, wherein the method refers to the non-commutative shift parameter space of co-dimension 2.Type: GrantFiled: March 29, 2019Date of Patent: May 26, 2020Assignee: radius co., ltd.Inventor: Tohru Kohda
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Publication number: 20190229972Abstract: In accordance with an embodiment of the present invention, a method for receiving a signal, comprising the estimation step for estimating time and frequency shifts that are embedded in the received signal, to cancel-out shifts, wherein the method refers to the non-commutative shift parameter space of co-dimension 2.Type: ApplicationFiled: March 29, 2019Publication date: July 25, 2019Inventor: Tohru KOHDA
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Patent number: 8786480Abstract: There is provided a data conversion method based on negative ?-map suited for an A/D converter or chaos generator, that is adapted to an integrated circuit and capable of providing stable operation of the circuit. The data conversion method based on negative ?-map includes a discrete time integrator 1 having an amplification coefficient s and a damping factor ?, a quantizer 2 connected in series to the discrete time integrator 1, and a feedback circuit connected from an output of the quantizer 2 to an input of the discrete time integrator 1.Type: GrantFiled: March 22, 2011Date of Patent: July 22, 2014Assignee: Japan Science and Technology AgencyInventors: Yoshihiko Horio, Kenya Jinno, Tohru Kohda, Kazuyuki Aihara
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Patent number: 8773295Abstract: There is provided a data conversion method based on ?-map suited for an A/D converter or chaos generator, that is adapted to an integrated circuit and capable of providing stable operation of the circuit. The data conversion method based on scale-adjusted ?-map includes a discrete time integrator 1 having an amplification coefficient s(1??) and a damping factor ?, a quantizer 2connected in series to the discrete time integrator 1, and a feedback circuit 3 connected from an output of the quantizer 2 to an input of the discrete time integrator 1.Type: GrantFiled: March 22, 2011Date of Patent: July 8, 2014Assignee: Japan Science and Technology AgencyInventors: Yoshihiko Horio, Kenya Jinno, Tohru Kohda, Kazuyuki Aihara
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Publication number: 20130027239Abstract: There is provided a data conversion method based on negative ?-map suited for an A/D converter or chaos generator, that is adapted to an integrated circuit and capable of providing stable operation of the circuit. The data conversion method based on negative ?-map includes a discrete time integrator 1 having an amplification coefficient s and a damping factor ?, a quantizer 2 connected in series to the discrete time integrator 1, and a feedback circuit connected from an output of the quantizer 2 to an input of the discrete time integrator 1.Type: ApplicationFiled: March 22, 2011Publication date: January 31, 2013Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Yoshihiko Horio, Kenya Jinno, Tohru Kohda, Kazuyuki Aihara
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Publication number: 20130015992Abstract: There is provided a data conversion method based on ?-map suited for an A/D converter or chaos generator, that is adapted to an integrated circuit and capable of providing stable operation of the circuit. The data conversion method based on scale-adjusted ?-map includes a discrete time integrator 1 having an amplification coefficient s(1??) and a damping factor ?, a quantizer 2 connected in series to the discrete time integrator 1, and a feedback circuit 3 connected from an output of the quantizer 2 to an input of the discrete time integrator 1.Type: ApplicationFiled: March 22, 2011Publication date: January 17, 2013Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Yoshihiko Horio, Kenya Jinno, Tohru Kohda, Kazuyuki Aihara
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Patent number: 8035668Abstract: An exposure apparatus which forms a pattern on an object. The apparatus includes an exposure head structure in which a plurality of elemental exposure units are arrayed, each elemental exposure unit including (i) at least one light source for emitting exposure light and (ii) an optical element which forms an image of the at least one light source on the object, for exposing the object. Positions of the images of the at least one light source in a direction perpendicular to a surface of the object include plural positions different from each other. A sensor detects a position of the surface of the object and produces a detection result. A controller receives the detection result and controls the exposure head structure such that a pattern is formed on the object by the exposure is selected to expose the object based on the detection result by the sensor.Type: GrantFiled: January 19, 2006Date of Patent: October 11, 2011Assignee: Canon Kabushiki KaishaInventors: Mitsuro Sugita, Kazuaki Ohmi, Takao Yonehara, Toshihiko Tsuji, Takaaki Terashi, Tohru Kohda, Shinji Tsutsui
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Publication number: 20110193734Abstract: A signal converter and the like, which can more accurately and stably realize signal conversion between an analog signal and a digital signal are proposed. In a ?-encoder, when a logic value generated by at least a quantizer 7 is 1, a signal generation unit 11 generates a feedback signal from an amplified signal generated by an amplifier 5 and a power source signal generated by a power source 9, and the signal generation unit 11 adds the feedback signal to an input signal. Therefore, for example, the ?-encoder having robustness to fluctuation of a quantizer 7 can be realized. Further, the more-stable ?-encoder can be realized by a negative ?-encoder that generates the feedback signal using a signal obtained by inverting a sign of the amplified signal. Optimum designs of the amplifier 5 and power source 9 can also be realized.Type: ApplicationFiled: August 21, 2009Publication date: August 11, 2011Applicants: JAPAN SCIENCE AND TECHNOLOGY AGENCY, KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORPORATIONInventors: Satoshi Hironaka, Tohru Kohda, Kazuyuki Aihara
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Patent number: 7994952Abstract: Provided is a highly accurate converter and the like that makes up for the instability of circuit elements, by focusing on a relationship between the Markov chain and ? conversion. A converter 1 that determines the decoded value of a sample value x based on L-bit number bi (i=1, . . . , L) includes a decoding section 3 to determine the decoded value xD for ?=1/? (where 1<?<2) using equation (eq 1). Further, the converter 1 also includes a matrix estimation section 5 to determine the Markov transition matrix based on bi. Unlike a conventional method that pays attention to the lower limit of an interval, the decoding section 3 using equation (eq 1) pays attention to the center of the interval, and this point is a significant difference. x D = ? i = 1 L ? b i ? ? i + ? L + 1 2 ? ( 1 - ? ) .Type: GrantFiled: July 17, 2008Date of Patent: August 9, 2011Assignees: Japan Science and Technology Agency, Kyushu University, National University CorporationInventors: Satoshi Hironaka, Tohru Kohda, Kazuyuki Aihara
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Publication number: 20100233377Abstract: An imprint apparatus which includes an imprint head configured to hold a mold, and performs an imprint process including dispensing of a resin to a shot region on a substrate and pressing of the mold and the dispensed resin with each other, comprises a controller configured to control an order of the imprint process for a plurality of selected shot regions on the substrate, and a first dispenser and a second dispenser configured to dispense the resin, wherein the first dispenser is arranged on a side of a first direction with respect to the imprint head, and the second dispenser is arranged on a side of a second direction opposite to the first direction with respect to the imprint head.Type: ApplicationFiled: March 11, 2010Publication date: September 16, 2010Applicant: CANON KABUSHIKI KAISHAInventors: Akio Aoki, Hiroshi Inada, Tohru Kohda, Hideki Ina, Hiroshi Sato
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Publication number: 20100207796Abstract: Provided is a highly accurate converter and the like that makes up for the instability of circuit elements, by focusing on a relationship between the Markov chain and ? conversion. A converter 1 that determines the decoded value of a sample value x based on L-bit number bi (i=1, . . . , L) includes a decoding section 3 to determine the decoded value xD for ?=1/? (where 1<?<2) using equation (eq1). Further, the converter 1 also includes a matrix estimation section 5 to determine the Markov transition matrix based on bi. Unlike a conventional method that pays attention to the lower limit of an interval, the decoding section 3 using equation (eq1) pays attention to the center of the interval, and this point is a significant difference. x D = ? i = 1 L ? b i ? ? i + ? L + 1 2 ? ( 1 - ? ) .Type: ApplicationFiled: July 17, 2008Publication date: August 19, 2010Applicants: JAPAN SCIENCE AND TECHNOLOGY AGENCY, KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORPORATIONInventors: Satoshi Hironaka, Tohru Kohda, Kazuyuki Aihara
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Publication number: 20060158504Abstract: An exposure apparatus which forms a pattern on an object includes an exposure head structure in which a plurality of elemental exposure units each including at least one light source and an optical element which forms an image of the light source on the object are arrayed, a sensor which detects the surface position of the object, and a controller which controls exposure by the exposure head structure based on the detection result by the sensor. The controller forms a pattern on the object while selectively operating one of the plurality of elemental exposure units, which satisfies a predetermined condition.Type: ApplicationFiled: January 19, 2006Publication date: July 20, 2006Inventors: Mitsuro Sugita, Kazuaki Ohmi, Takao Yonehara, Toshihiko Tsuji, Takaaki Terashi, Tohru Kohda, Shinji Tsutsui
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Publication number: 20050206867Abstract: A scanning exposure apparatus includes an illumination optical system for illuminating a pattern on a mask using arc-shaped illumination light, a projection optical system for projecting the pattern on the mask illuminated by the illumination optical system onto a plate, a mask stage for scanning the mask, a plate stage for scanning the plate, the scanning exposure apparatus scanning the mask stage and plate stage synchronously relative to the projection optical system, a mask support mechanism for supporting a periphery of the mask, and a mask stage tilt mechanism for arranging the pattern in an area illuminated by the arc-shaped illumination light in an object-surface-side focal plane of the projection optical system, wherein the mask deforms due to its own weight from the peripheral support.Type: ApplicationFiled: May 18, 2005Publication date: September 22, 2005Applicant: CANON KABUSHIKI KAISHAInventors: Tohru Kohda, Shinji Tsutsui
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Patent number: 6947122Abstract: A scanning exposure apparatus includes an illumination optical system for illuminating a pattern on a mask using arc-shaped illumination light, a projection optical system for projecting the pattern on the mask illuminated by the illumination optical system onto a plate, a mask stage for scanning the mask, a plate stage for scanning the plate, the scanning exposure apparatus scanning the mask stage and plate stage synchronously relative to the projection optical system, a mask support mechanism for supporting a periphery of the mask, and a mask stage tilt mechanism for arranging the pattern in an area illuminated by the arc-shaped illumination light in an object-surface-side focal plane of the projection optical system, wherein the mask deforms due to its own weight from the peripheral supported.Type: GrantFiled: June 24, 2003Date of Patent: September 20, 2005Assignee: Canon Kabushiki KaishaInventors: Tohru Kohda, Shinji Tsutsui
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Publication number: 20040001191Abstract: A scanning exposure apparatus includes an illumination optical system for illuminating a pattern on a mask using arc-shaped illumination light, a projection optical system for projecting the pattern on the mask illuminated by the illumination optical system onto a plate, a mask stage for scanning the mask, a plate stage for scanning the plate, the scanning exposure apparatus scanning the mask stage and plate stage synchronously relative to the projection optical system, a mask support mechanism for supporting a peripheral of the mask, and a mask stage tilt mechanism for arranging the pattern in an area illuminated by the arc-shaped illumination light in an object-surface-side focal plane of the projection optical system, wherein the mask deforms due to its own weight from the peripheral supported.Type: ApplicationFiled: June 24, 2003Publication date: January 1, 2004Applicant: Canon Kabushiki KaishaInventors: Tohru Kohda, Shinji Tsutsui
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Patent number: 6014445Abstract: An enciphering apparatus embodying this invention comprises chaos generation means for generating a real-valued sequence along a chaotic orbit in accordance with a predetermined number of first common keys and a predetermined nonlinear map, bit generation means for performing predetermined binarization on each real value in the generated real-valued sequence based on a predetermined number of second common keys to generate a binary sequence, and logic operation means for executing a predetermined logic operation on a binary sequence of an input plaintext and the generated keystream sequence bit by bit to generate a binary sequence of a ciphertext. For example, the first common keys are an initial seed of a nonlinear map and a value of a parameter k, and the bit generation means acquires plural pieces of binary data for each real value in the real-valued sequence using values indicated by a plurality of second keys as thresholds and obtains exclusive OR of those binary data.Type: GrantFiled: October 22, 1996Date of Patent: January 11, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Tohru Kohda, Akio Tsuneda