Patents by Inventor Tohru Komatsu

Tohru Komatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050116138
    Abstract: The reliability and production yield of a solid state image sensing device is improved. Over a surface of a wiring substrate, a sensor chip and a lens-barrel having the sensor chip housed therein are mounted. To the lens-barrel, a lens holder for retaining a lens is connected. Over a back surface of the wiring substrate, a logic chip, a memory chip and a passive part are mounted, and they are sealed with a sealing resin. The lens-barrel and lens holder are each threaded. They are thermally welded while the threads are fitted to each other. The passive part is bonded to the wiring substrate via a Sn—Ag type Pb-free solder. After the wiring substrate is subjected to plasma washing treatment, the sensor chip is mounted over the wiring substrate and an electrode pad of the sensor chip and an electrode of the wiring substrate are electrically connected via a bonding wire.
    Type: Application
    Filed: September 22, 2004
    Publication date: June 2, 2005
    Inventors: Kenji Hanada, Masaki Nakanishi, Kunio Shigemura, Takaomi Nishi, Koji Shida, Izumi Tezuka, Shunichi Abe, Yoshihiro Tomita, Mitsuaki Seino, Tohru Komatsu
  • Patent number: 6352628
    Abstract: A refractory metal silicide target is characterized by comprising a fine mixed structure composed of MSi2 (where M: refractory metal) grains and Si grains, wherein the number of MSi2 grains independently existing in a cross section of 0.01 mm2 of the mixed structure is not greater than 15, the MSi2 grains have an average grain size not greater than 10 &mgr;m, whereas free Si grains existing in gaps of the MSi2 grains have a maximum grain size not greater than 20 &mgr;m. The target has a high density, high purity fine mixed structure with a uniform composition and contains a small amount of impurities such as oxygen etc. The employment of the target can reduce particles produced in sputtering, the change of a film resistance in a wafer and the impurities in a film and improve yield and reliability when semiconductors are manufactured.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: March 5, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michio Sato, Takashi Yamanobe, Tohru Komatsu, Yoshiharu Fukasawa, Noriaki Yagi, Toshihiro Maki, Hiromi Shizu
  • Publication number: 20010037938
    Abstract: A refractory metal silicide target is characterized by comprising a fine mixed structure composed of MSi2 (where M: refractory metal) grains and Si grains, wherein the number of MSi2 grains independently existing in a cross section of 0.01 mm2 of the mixed structure is not greater than 15, the MSi2 grains have an average grain size not greater than 10 &mgr;m, whereas free Si grains existing in gaps of the MSi2 grains have a maximum grain size not greater than 20 &mgr;m. The target has a high density, high purity fine mixed structure with a uniform composition and contains a small amount of impurities such as oxygen etc. The employment of the target can reduce particles produced in sputtering, the change of a film resistance in a wafer and the impurities in a film and improve yield and reliability when semiconductors are manufactured.
    Type: Application
    Filed: May 2, 2001
    Publication date: November 8, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Michio Sato, Takashi Yamanobe, Tohru Komatsu, Yoshiharu Fukasawa, Noriaki Yagi, Toshihiro Maki, Hiromi Shizu
  • Patent number: 6309593
    Abstract: A refractory metal silicide target is characterized by comprising a fine mixed structure composed of MSi2 (where M: refractory metal) grains and Si grains, wherein the number of MSi2 grains independently existing in a cross section of 0.01 mm2 of the mixed structure is not greater than 15, the MSi2 grains have an average grain size not greater than 10 &mgr;m, whereas free Si grains existing in gaps of the MSi2 grains have a maximum grain size not greater than 20 &mgr;m. The target has a high density, high purity fine mixed structure with a uniform composition and contains a small amount of impurities such as oxygen etc. The employment of the target can reduce particles produced in sputtering, the change of a film resistance in a wafer and the impurities in a film and improve yield and reliability when semiconductors are manufactured.
    Type: Grant
    Filed: March 20, 1995
    Date of Patent: October 30, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Michio Sato, Takashi Yamanobe, Tohru Komatsu, Yoshiharu Fukasawa, Noriaki Yagi, Toshihiro Maki, Hiromi Shizu