Patents by Inventor Tohru Koyama

Tohru Koyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6677760
    Abstract: A method of and apparatus for analyzing a failure is provided. A laser beam generator (1) has a plurality of laser beam sources differing in wavelength from each other. First, the laser beam generator (1) generates a laser beam (B1) of about 1.1 &mgr;m in wavelength, and a failure analyzer (6) stores therein a resultant first current image. Next, the laser beam generator (1) generates a laser beam (B1) of about 1.3 &mgr;m in wavelength, and the failure analyzer (6) stores therein a resultant second current image. Next, the laser beam generator (1) generates a laser beam (B1) of not less than 2.0 &mgr;m in wavelength, and the failure analyzer (6) stores therein a resultant third current image. The failure analyzer (6) analyzes the cause and site of a failure in a sample (3) by reference to the first to third current images stored therein. The method can diagnose and localize the failure in a chip by reference to only the current images obtained by the laser beam irradiation.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: January 13, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Tohru Koyama
  • Patent number: 6678623
    Abstract: A failure analysis device is provided which can realize automatic light emission analysis even when the tested chips have logic LSIs etc. fabricated therein. A comparator (11) compares individual Iddq values (I1) to (In) sequentially provided from a probe card (3) with a threshold (Ith1) provided from a main control unit (7). An abnormality occurrence vector specifying unit (8) receives data (D2) about the results of comparison from the comparator (11) and specifies an abnormality occurrence vector or vectors from among a plurality of test vectors (TB1) to (TBn) on the basis of the data (D2). More specifically, the abnormality occurrence vector specifying unit (8) specifies the test vector as the abnormality occurrence vector when the corresponding detected Iddq value is larger than the threshold (Ith1).
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: January 13, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Tohru Koyama
  • Patent number: 6614049
    Abstract: A dummy pattern layer, which has not been effectively used, included in upper wire layers of a memory part of a system LSI chip is utilized as a large-scale wire TEG (test element group) region while leaving a dummy pattern function. Thus, the system LSI chip is provided with the wire TEG region independent of a product region while keeping the product region.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: September 2, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tohru Koyama
  • Publication number: 20030129467
    Abstract: The object of this invention is to provide a solid polymer electrolyte which is excellent in durability and of low cost, and membranes, solutions for electrode catalyst coating, membrane/electrode assemblies and fuel cells which use the electrolyte. According to this invention, there can be provided a fuel cell which comprises an electrode assembly having an electrode catalyst membrane formed therein, said catalyst membrane comprising a polymer electrolyte membrane held between an anode on one side of the principal plane of the electrolyte membrane and a cathode on the other side of the principal lane thereof, current collecting plates provided each independently in close contact, to the anode side and the cathode side of the electrode assembly, and electroconductive separators having gas supply passages to the anode and to the cathode provided on the outside surfaces of the current collecting plates.
    Type: Application
    Filed: June 24, 2002
    Publication date: July 10, 2003
    Applicant: HITACHI, LTD.
    Inventors: Makoto Morishima, Tomoichi Kamo, Toshiyuki Kobayashi, Kenji Yamaga, Tohru Koyama
  • Publication number: 20030115939
    Abstract: A scanning probe microscope includes a laser diode (1a) as a light source for emitting light lower in energy level than band gap of semiconductor as a sample.
    Type: Application
    Filed: July 12, 2002
    Publication date: June 26, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yukari Imai, Mari Tsugami, Hitoshi Maeda, Tohru Koyama
  • Publication number: 20030118886
    Abstract: The object of this invention is to provide a solid polymer electrolyte which is excellent in durability and of low cost, and membranes, solutions for electrode catalyst coating, membrane/electrode assemblies and fuel cells which use the electrolyte. According to this invention, there can be provided a fuel cell which comprises an electrode assembly having an electrode catalyst membrane formed therein, said catalyst membrane comprising a polymer electrolyte membrane held between an anode on one side of the principal plane of the electrolyte membrane and a cathode on the other side of the principal lane thereof, current collecting plates provided each independently in close contact, to the anode side and the cathode side of the electrode assembly, and electroconductive separators having gas supply passages to the anode and to the cathode provided on the outside surfaces of the current collecting plates.
    Type: Application
    Filed: February 25, 2002
    Publication date: June 26, 2003
    Inventors: Makoto Morishima, Tomoichi Kamo, Toshiyuki Kobayashi, Kenji Yamaga, Tohru Koyama
  • Publication number: 20030096149
    Abstract: An object of the present invention is to provide a highly durable solid polymer electrolyte that has a deterioration resistance equal to or higher than that of the fluorine-containing solid polymer electrolytes or a deterioration resistance sufficient for practical purposes, and can be produced at a low cost. According to the present invention, there is provided a solid polymer electrolyte comprising a polyether ether sulfone that is used as a electrolyte and has sulfoalkyl groups bonded to its aromatic rings and represented by the general formula —(CH2)n—SO3H.
    Type: Application
    Filed: July 31, 2002
    Publication date: May 22, 2003
    Inventors: Tohru Koyama, Toshiyuki Kobayashi, Kenji Yamaga, Tomoichi Kamo, Kazutoshi Higashiyama
  • Publication number: 20030082429
    Abstract: The object of this invention is to provide an electrode for a polymer electrolyte fuel cell, a separator therefor, a polymer electrolyte fuel cell and a generating system, which electrode is simplified in structure, have high handling property, can be transferred precisely to a predetermined position, and enables automation of a production process.
    Type: Application
    Filed: February 21, 2002
    Publication date: May 1, 2003
    Inventors: Katsunori Nishimura, Masahiro Komachiya, Jinichi Imahashi, Tohru Koyama, Tomoichi Kamo
  • Publication number: 20020111759
    Abstract: A failure analysis device is provided which can realize automatic light emission analysis even when the tested chips have logic LSIs etc. fabricated therein. A comparator (11) compares individual Iddq values (I1) to (In) sequentially provided from a probe card (3) with a threshold (Ith1) provided from a main control unit (7). An abnormality occurrence vector specifying unit (8) receives data (D2) about the results of comparison from the comparator (11) and specifies an abnormality occurrence vector or vectors from among a plurality of test vectors (TB1) to (TBn) on the basis of the data (D2). More specifically, the abnormality occurrence vector specifying unit (8) specifies the test vector as the abnormality occurrence vector when the corresponding detected Iddq value is larger than the threshold (Ith1).
    Type: Application
    Filed: July 19, 2001
    Publication date: August 15, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Tohru Koyama
  • Patent number: 6009545
    Abstract: Data containing defect position coordinates obtained based on the result of physical inspection of foreign material, a defect or the like at the surface of a semiconductor wafer by a defect inspecting apparatus is stored. Also stored is data of physical coordinates obtained based on fail bit data from a tester. Data indicating an additional failure region is produced by an additional failure region estimating apparatus based on the fail bit data, and is stored. Collation produces data of corrected physical position coordinates by adding the stored data of limitation by failure mode to the stored data of physical position coordinates, and collates the data of corrected physical position coordinates with stored data of defect position coordinates. Accordingly, accuracy in collation is improved, and failure can be analyzed even if caused not by a defect located at an address of the failure obtained by the fail bit data but by a defect relating to the defect located at the address of a failure.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: December 28, 1999
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Toshikazu Tsutsui, Tohru Koyama, Fumihito Ohta, Yasukazu Mukogawa, Masaaki Furuta, Yohji Mashiko
  • Patent number: 5982056
    Abstract: A highly thermal-conductive and thermal-resistant electrically insulated coil with less outflow of a thermosetting resin composition can be produced, to provide a small-scale, light-weight rotating machine with high power. The thermosetting resin composition comprises (a) a polyfunctional epoxy resin containing three or more p-(2,3-epoxypropoxy) phenyl groups and a group represented by the Chemical formula 1; or an epoxy resin with a naphthalene backbone, represented by the Chemical formula 3, 4 or 5 or an epoxy resin with an anthracene backbone, such as diglycidyl ether of anthracene diol and triglycidyl ether of anthracene triol; (b) a bifunctional epoxy resin containing two p-(2,3-epoxypropoxy) phenyl groups; (c) an acid anhydride curing agent; and (d) a metal acetonate curing catalyst represented by the Chemical formula 2 at 0.1 to 5 parts by weight per 100 parts by weight of the epoxy resins.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: November 9, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Tohru Koyama, Katsuo Sugawara, Shoichi Maruyama, Ikushi Kano, Yoshikiyo Kashiwamura
  • Patent number: 5952837
    Abstract: A sample to be measured having a semiconductor integrated circuit having interconnection lines is set on a scanning photoinduced current analyzer with one end of the interconnection line being open and the other end connected through a current amplifier to the ground. When a laser beam falls on part having a comparatively low thermal conductivity, such as a part having a void, of the interconnection line while the interconnection line is scanned with the laser beam, temperature distribution in the interconnection line changes at the part. The change in temperature distribution produces spontaneous thermoelectromotive force by the Seebeck effect to induce a current. The current amplifier amplifies the induced current, and then an image date converter converts the amplified current into image information in synchronism with the scanning operation of the laser beam.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: September 14, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tohru Koyama
  • Patent number: 5844850
    Abstract: Data containing defect position coordinates obtained based on the result of physical inspection of a foreign material, a defect and the like at a surface of a semiconductor wafer by a defect inspecting apparatus is stored in storage means. Data of physical position coordinates obtained based on fail bit data from a tester is stored in storage means. Data indicating an additional failure region is produced by additional failure region estimating means based on the fail bit data, and is stored in storage means. Collating means produces data of corrected physical position coordinates by adding the data of limitation by failure mode stored in storage means to the data of physical position coordinates stored in storage means, and collates the data of corrected physical position coordinates with data of defect position coordinates stored in storage means.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: December 1, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Toshikazu Tsutsui, Tohru Koyama, Fumihito Ohta, Yasukazu Mukogawa, Masaaki Furuta, Yohji Mashiko
  • Patent number: 5760892
    Abstract: A method of analyzing a failure of semiconductor device by using an emission microscope for easy analysis of current leakage is disclosed. Light emission information is stored in X/Y memory spaces (16), with a Z direction indicating an emitted light intensity. A light emission presence bit (17) in the light emission information means a bit for which light emission is judged as being present, and the number of light emission presence bits is determined on the basis of the emitted light intensity. An image memory (11) has a three-dimensional memory space including an X/Y space indicative of plane positions of light emitting portions and a Z space indicative of the emitted light intensity. The position and intensity of light emission are detected by searching the light emission information stored in the image memory (11) to analyze the failure.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: June 2, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tohru Koyama
  • Patent number: 5733402
    Abstract: In the production of electrically insulated coils which make up insulating layers, insulating material is wound around an electric conductor to form an insulating substrate, then impregnating varnish consisting of thermosetting resin is applied to the insulating substrate and hardened. In this electrically insulated coil production method, the impregnating varnish is made up of acid anhydride setting epoxy resin elements that include latent accelerators. These accelerators take more than 30 days to increase their initial viscosity by three times during storage at 25 degrees centigrade. After the insulating substrate is impregnated with the varnish, the substrate is heated at a temperature which will cause the impregnating varnish on the surface of the insulating substrate to lose its fluidity in under 30 minutes in order to preset the varnish.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: March 31, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Katsuo Sugawara, Tohru Koyama, Syoichi Maruyama
  • Patent number: 5708371
    Abstract: A sample to be measured having a semiconductor integrated circuit having interconnection lines is set on a scanning photoinduced current analyzer with one end of the interconnection line connected to a ground and the other end connected through a current amplifier to the ground. When a laser beam falls on part having a comparatively low thermal conductivity, such as a part having a void, of the interconnection line while the interconnection line is scanned with the laser beam, temperature distribution in the interconnection line changes at the part. The change in temperature distribution produces spontaneous thermoelectromotive force by the Seebeck effect to induce a current. The current amplifier amplifies the induced current, and then an image date converter converts the amplified current into image information in synchronism with the scanning operation of the laser beam.
    Type: Grant
    Filed: July 18, 1995
    Date of Patent: January 13, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tohru Koyama
  • Patent number: 5381032
    Abstract: A semiconductor device without erroneous operation and deterioration of characteristics in a transistor even when an impurity region is formed in self-alignment by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. This semiconductor device includes a gate electrode formed of a polycrystal silicon layer 4b having the crystal orientation of the crystal grains arranged in a definite orientation. By implanting ions at a predetermined angle with respect to the crystallographic axis of the crystal grains of the polycrystal silicon layer 4b in forming a p.sup.+ impurity region 5 by ion implantation using the gate electrode as a mask, the channeling phenomenon where ions pass through the gate electrode is prevented. Therefore, generation of erroneous operation and deterioration of characteristics in a transistor are prevented in forming an impurity region in self-alignment by ion implantation using the gate electrode as a mask.
    Type: Grant
    Filed: August 26, 1993
    Date of Patent: January 10, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshiko Kokawa, Tohru Koyama, Kenji Kusakabe, Katsuhiko Tamura, Yasuna Nakamura
  • Patent number: 5324767
    Abstract: A thermoplastic resin composition for casting high-voltage coils containing two kinds of fillers (A) and (B), and products as molded coils and panels obtained by casting and curing the composition.The composition of the present invention contains 60%-85% by weight, based on the total weight of the composition, of a silica type filler which is an admixture (A) a spherical silica having an average particle diameter of 0.1-0.9 .mu.m and (B) a ground silica having an average particle diameter of 3-9 .mu., the ratio A/(A+B) being 1%-7% by weight.Products as molded coils and panels prepared by using the composition have good resistance to cracking and resistance to moisture.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: June 28, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Tohru Koyama, Hirokazu Takasaki, Hiroshi Suzuki, Shigeo Amagi, Akio Mukoh, Ikushi Kano
  • Patent number: 5221630
    Abstract: A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.
    Type: Grant
    Filed: October 16, 1992
    Date of Patent: June 22, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tohru Koyama, Katsuhiko Tamura, Yasuna Nakamura, Yoshiko Kokawa, Kenji Kusakabe
  • Patent number: 5177569
    Abstract: A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.
    Type: Grant
    Filed: November 8, 1991
    Date of Patent: January 5, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tohru Koyama, Katsuhiko Tamura, Yasuna Nakamura, Yoshiko Kokawa, Kenji Kusakabe