Abstract: There is provided a semiconductor memory device for preventing an increase of a cell area of a Shadow RAM comprising a portion of an SRAM memory cell and a ferroelectric capacitor connected to a storage node of the portion of the SRAM memory cell and achieving high capacitance formation of a storage capacitor. The Shadow RAM is provided with a relay wiring layer between a wiring layer corresponding to the storage node and a lower electrode of the ferroelectric capacitor, a wiring corresponding to the storage node is connected to a relay wiring via a first and a second opening portion arranged at a first interval and the lower electrode of the ferroelectric capacitor is connected to a relay wiring via a third and a fourth opening portion arranged at a second interval narrower than the first interval.

Abstract: In a shadow RAM using a ferroelectric capacitor, a memory cell constituted by connecting a ferroelectric capacitor directly to each of storage nodes of an unloaded four-transistor SRAM cell formed of four transistors. Thus, the number of transistors per one memory cell can be reduced by two transistors, so that a storage capacity can be increased further.

Abstract: In a shadow RAM using a ferroelectric capacitor, a memory cell constituted by connecting a ferroelectric capacitor directly to each of storage nodes of an unloaded four-transistor SRAM cell formed of four transistors. Thus, the number of transistors per one memory cell can be reduced by two transistors, so that a storage capacity can be increased further.

Abstract: For a memory cell comprising: a pair of memory nodes for holding a pair of complementary voltages; a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line; and a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, storing operation of the memory cell is carried out by swinging the voltage of the plate line between a first voltage that is higher than power supply voltage of the memory cell and a second voltage that is lower than the ground potential while keeping the switching elements in off states, thereby remanent polarization of the ferroelectric capacitors is made larger.

Abstract: In a shadow RAM using a ferroelectric capacitor, a memory cell constituted by connecting a ferroelectric capacitor directly to each of storage nodes of an unloaded four-transistor SRAM cell formed of four transistors. Thus, the number of transistors per one memory cell can be reduced by two transistors, so that a storage capacity can be increased further.

Abstract: There is provided a semiconductor memory device for preventing an increase of a cell area of a Shadow RAM comprising a portion of an SRAM memory cell and a ferroelectric capacitor connected to a storage node of the portion of the SRAM memory cell and achieving high capacitance formation of a storage capacitor. The Shadow RAM is provided with a relay wiring layer between a wiring layer corresponding to the storage node and a lower electrode of the ferroelectric capacitor, a wiring corresponding to the storage node is connected to a relay wiring via a first and a second opening portion arranged at a first interval and the lower electrode of the ferroelectric capacitor is connected to a relay wiring via a third and a fourth opening portion arranged at a second interval narrower than the first interval.

Abstract: In a shadow RAM using a ferroelectric capacitor, a memory cell constituted by connecting a ferroelectric capacitor directly to each of storage nodes of an unloaded four-transistor SRAM cell formed of four transistors. Thus, the number of transistors per one memory cell can be reduced by two transistors, so that a storage capacity can be increased further.

Abstract: For a memory cell comprising: a pair of memory nodes for holding a pair of complementary voltages; a pair of switching elements for controlling the connection between each memory node and a bit line corresponding to the memory node according to ON/OFF control by a common word line; and a pair of ferroelectric capacitors each of which is connected to a plate line and corresponding one of the memory nodes, storing operation of the memory cell is carried out by swinging the voltage of the plate line between a first voltage that is higher than power supply voltage of the memory cell and a second voltage that is lower than the ground potential while keeping the switching elements in off states, thereby remanent polarization of the ferroelectric capacitors is made larger.

Abstract: A shadow RAM cell and a non-volatile memory employing a ferroelectric capacitor, and a control method therefor can reduce number of transistors forming a memory cell to permit increasing of capacity comparable with SRAM. The a memory cell includes a flip-flop having a pair of storage nodes, a pair of switching elements controlled ON and OFF by a common word line and controlling connection between a pair of storage nodes and a pair of bit lines, and a pair of ferroelectric capacitors directly connected to the pair of storage nodes at respective one ends and connected to a plate line at the other end.

Abstract: A ferroelectric random access memory device stores a data bit in a pair of ferroelectric capacitors in the form of remanence varied along a hysteresis loop, and a sense amplifier increases the magnitude of a potential difference produced on a bit line pair due to the remanence, wherein the insensible voltage range of the sense amplifier is intentionally increased in a life test for the pair of ferroelectric capacitors so as to screen out a short-lived ferroelectric capacitor.

Abstract: A nonvolatile semiconductor memory device using a ferroelectric memory includes memory cells having two ferroelectric capacitors and two MOS transistors. The memory device includes a switching circuit that reverses the polarity, or sign, of data when previously-read data is written back into the memory cell. A toggle bit memory stores a toggle bit representing the sign of the data that was switched by the switching circuit. The semiconductor memory device has a resetting circuit that returns the reversed-sign data to its normal state using the switching circuit, based on the data read from the memory cell and the toggle bit read from the toggle bit memory.

Abstract: A current differential amplifier circuit comprises first and second pMOS transistors (P11 and P12) connected between a power supply and a first node (W11 ); third and fourth pMOS transistors (P13 and P14) connected between the power supply and a second node (W12); a fifth pMOS transistor (P15) connected between gates of the second and the third pMOS transistors (P12 and P13), each of the gates connected to its opposite node (W11 or W12 ); a first nMOS transistor (N16) connected between the first node (W11 ) and a first current source (I11 ) and having its gate connected to the second node (W12); and a second nMOS transistor (N17) connected between the second node (W12) and a second current source (I12) and having its gate connected to the first node (W11). Pre-charge signal (/PC) is applied to the gates of the first, fourth and the fifth pMOS transistors (P11, P14 and P15) and comparison results are derived from either the first node (W11) or the second node (W12).

Abstract: A content addressable memory system includes one retrieval sense amplifier provided in common with a plurality of memory words. A logic operation between a result of retrieval outputted from the sense amplifier and the result of a preceding retrieval stored in a one-bit working register provided for the same sense amplifier is carried out by a control gate also provided for the same sense amplifier, and the result of the logic operation is stored back in the same working register. A plurality of working registers may be provided for each control gate and sense amplifier. The content addressable memory system can retrieve a variable word length data and can be realized with a reduced circuit area.

Abstract: A semiconductor associative memory device directly supplies status signals each representative of matching state or mismatching state from regular/redundant memory words to an address generator for generating a preliminary address signal representative of the regular/redundant memory word supplying the status signal representative of the matching state, and an address correcting system examines the preliminary address signal to see whether or not the preliminary address signal is representative of one of the regular/redundant memory word affected by a replacement of a defective regular memory word with the redundant memory word; when the preliminary address signal is representative of the regular/redundant memory word, the address correcting system generates a formal address signal representative of the address of one of the regular memory words expected to store the data code matched with a given data code if all the regular memory words are excellent at storing data codes.

Abstract: A non-volatile semiconductor memory having a redundant memory cell row and a row address selector. During one of read and write operations, the row address selector outputs a regular row address signal from a row address signal buffer as the selected row signal. During an erase operation, the row address selector outputs a defective row address signal from a defective row address memory as the selected row signal, and a row decoder unit provides an erase preventing voltage to one of unused word line and unused redundant word line according to the selected row address signal, a redundant row use flag signal, and a substitution signal to prevent the erasing of unused memory cells.

Abstract: The non-volatile memory includes (A) a cell array including (a) memory cells arranged to form rows and columns, each cell having first and second transistors which commonly have a floating gate, (b) first and second gate lines, each connected with gates of the first and second transistors of the memory cells disposed in each of the rows and columns, respectively, (c) first and second drain lines, each connected with drains of the first and second transistors of the memory cells disposed in each of the columns and rows, respectively, and (d) source lines, each connected with sources of the first and second transistors, (B) a first voltage supplier for applying a first or second voltage to each of the first gate lines in accordance with a first input signal, (C) a detector for detecting a current running through the first drain lines and further transmitting a first output signal, (D) a second voltage supplier for applying a first or second voltage to each of the second gate lines in accordance with a second in