Abstract: An underwater positioning system for accurate underwater positioning. At least one among at least one acoustic transmitter and at least one hydrophone is provided at known coordinates and which positions an unknown point having unknown coordinates at which another acoustic transmitter or hydrophone is provided, includes a time window that stores in advance, when the unknown point is set in a plurality of regions set by dividing an underwater positioning range, a time window for a sound wave emitted from the acoustic transmitter to reach the hydrophone for each of the regions, and a coordinate estimation and specification unit that calculates for each of the regions a time window-applied impulse response as an inner product of the time window and an impulse response of a sound wave propagation path from the acoustic transmitter to the hydrophone and estimates that the unknown point is located in the region where the energy of the time window-applied impulse response is maximized.

Abstract: An output circuit has: a first driver circuit configured to receive a voltage of an input terminal and output a first voltage to an output terminal; a first comparison circuit configured to compare a first reference voltage with a voltage of the output terminal; a second driver circuit configured to receive the voltage of the input terminal and output a second voltage to the output terminal and become an off state according to a comparison result of the first comparison circuit; a second comparison circuit configured to compare a second reference voltage different from the first reference voltage with the voltage of the output terminal; and a third driver circuit configured to receive the voltage of the input terminal and output a third voltage to the output terminal and become an off state according to a comparison result of the second comparison circuit.

Abstract: An output circuit has: a first driver circuit configured to receive a voltage of an input terminal and output a first voltage to an output terminal; a first comparison circuit configured to compare a first reference voltage with a voltage of the output terminal; a second driver circuit configured to receive the voltage of the input terminal and output a second voltage to the output terminal and become an off state according to a comparison result of the first comparison circuit; a second comparison circuit configured to compare a second reference voltage different from the first reference voltage with the voltage of the output terminal; and a third driver circuit configured to receive the voltage of the input terminal and output a third voltage to the output terminal and become an off state according to a comparison result of the second comparison circuit.

Abstract: An output circuit has: a first driver circuit configured to receive a voltage of an input terminal and output a first voltage to an output terminal; a first comparison circuit configured to compare a first reference voltage with a voltage of the output terminal; a second driver circuit configured to receive the voltage of the input terminal and output a second voltage to the output terminal and become an off state according to a comparison result of the first comparison circuit; a second comparison circuit configured to compare a second reference voltage different from the first reference voltage with the voltage of the output terminal; and a third driver circuit configured to receive the voltage of the input terminal and output a third voltage to the output terminal and become an off state according to a comparison result of the second comparison circuit.

Abstract: An output circuit has: a first driver circuit configured to receive a voltage of an input terminal and output a first voltage to an output terminal; a first comparison circuit configured to compare a first reference voltage with a voltage of the output terminal; a second driver circuit configured to receive the voltage of the input terminal and output a second voltage to the output terminal and become an off state according to a comparison result of the first comparison circuit; a second comparison circuit configured to compare a second reference voltage different from the first reference voltage with the voltage of the output terminal; and a third driver circuit configured to receive the voltage of the input terminal and output a third voltage to the output terminal and become an off state according to a comparison result of the second comparison circuit.

Abstract: A semiconductor device has an analog switch, in which a P channel transistor and an N channel transistor are connected in parallel between an input terminal and an output terminal; a variable voltage circuit, which variably generates, according to an input voltage applied to the input terminal, potentials of a first gate voltage and first back gate voltage of the P channel transistor and of a second gate voltage and second back gate voltage of the N channel transistor; and a control circuit, which supplies to the variable voltage circuit a control signal controlling the analog switch to be conducting or non-conducting. In response to the control signal causing the analog switch to be conducting, the variable voltage circuit outputs the variable-generated first gate voltage and second gate voltage to the respective gates of the P channel transistor and N channel transistor.

Abstract: A semiconductor device has an analog switch, in which a P channel transistor and an N channel transistor are connected in parallel between an input terminal and an output terminal; a variable voltage circuit, which variably generates, according to an input voltage applied to the input terminal, potentials of a first gate voltage and first back gate voltage of the P channel transistor and of a second gate voltage and second back gate voltage of the N channel transistor; and a control circuit, which supplies to the variable voltage circuit a control signal controlling the analog switch to be conducting or non-conducting. In response to the control signal causing the analog switch to be conducting, the variable voltage circuit outputs the variable-generated first gate voltage and second gate voltage to the respective gates of the P channel transistor and N channel transistor.

Abstract: An integrated circuit includes an analog signal output unit which converts a digital output signal into at least one analog output signal, and outputs the at least one analog output signal, an analog signal input unit which converts at least one analog input signal received from an exterior into a digital input signal, a switch circuit which provides at least one signal path through which the at least one analog output signal is supplied from the analog signal output unit to the analog signal input unit as the at least one analog input signal, and an offset adjustment control circuit which supplies an output offset from the analog signal output unit to the analog signal input unit via the at least one signal path so as to detect the digital input signal inclusive of the output offset and an input offset, and cancels offsets of the analog signal output unit and the analog signal input unit in response to the output offset and the input offset obtained from the detected digital input signal.

Abstract: First and second switches are connected at each node between adjacent resistors in a resistor row and at the end of the resistor row. A predetermined number of first switches are grouped together and short-circuited to obtain a plurality of first switch groups, and a predetermined number of second switches are grouped together and short-circuited to obtain a plurality of second switch groups. The first and second switch groups are connected to output terminals via output switches. The first and second switches are ON/OFF controlled such that only one switch in the first and second switch groups is connected to the resistance row.

Abstract: An integrated circuit includes an analog signal output unit which converts a digital output signal into at least one analog output signal, and outputs the at least one analog output signal, an analog signal input unit which converts at least one analog input signal received from an exterior into a digital input signal, a switch circuit which provides at least one signal path through which the at least one analog output signal is supplied from the analog signal output unit to the analog signal input unit as the at least one analog input signal, and an offset adjustment control circuit which supplies an output offset from the analog signal output unit to the analog signal input unit via the at least one signal path so as to detect the digital input signal inclusive of the output offset and an input offset, and cancels offsets of the analog signal output unit and the analog signal input unit in response to the output offset and the input offset obtained from the detected digital input signal.

Abstract: First and second switches are connected at each node between adjacent resistors in a resistor row and at the end of the resistor row. A predetermined number of first switches are grouped together and short-circuited to obtain a plurality of first switch groups, and a predetermined number of second switches are grouped together and short-circuited to obtain a plurality of second switch groups. The first and second switch groups are connected to output terminals via output switches. The first and second switches are ON/OFF controlled such that only one switch in the first and second switch groups is connected to the resistance row.

Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.

Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.

Abstract: An evaluation circuit 16 repeats processing in which an output VD thereof is reset, there is obtained repeatedly given times a difference between sampled output voltages Vo of a replica circuit 11R when respective times t1 and t2 have elapsed after a voltage Vi is step-inputted to the replica circuit 11R, and the differences are successively summed. A comparator circuit 20 compares a difference cumulation voltage VD with a reference voltage VS. A bias adjustment circuit 15 steps up the bias currents of the replica circuit 11R and an adjusted circuit 11 at every this given times if VD>VS, and ceases the adjustment if VD<VS.