Patents by Inventor Tohru Mogami

Tohru Mogami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10340399
    Abstract: Provided is an optical device in which an Si cap layer is provided on a Ge layer, and which is capable of effectively reducing dark current, while having a good effect on prevention of production line contamination by Ge. One embodiment of the optical device according to the present invention is provided with: a semiconductor layer which contains Ge and has a (001) surface and a facet surface between the (001) surface and a (110) surface; and a cap layer which is formed from Si, and which is formed on the (001) surface and the facet surface of the semiconductor layer. The ratio of the film thickness of the cap layer on the facet surface to the film thickness of the cap layer on the (001) surface is 0.4 or more; and the film thickness of the cap layer on the (001) surface is from 9 nm to 30 nm (inclusive).
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: July 2, 2019
    Assignee: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shigekazu Okumura, Tohru Mogami, Keizo Kinoshita, Tsuyoshi Horikawa, Junichi Fujikata
  • Patent number: 10247882
    Abstract: Provided is an optical waveguide circuit avoiding the difficulty of the property compensation based on temperature control, compensated with respect to the property variations due to fabrication error, particularly paid attention in a silicon waveguide, and being low in power consumption and high in performances. The optical waveguide circuit includes a silicon (Si) substrate, a buried oxide film (BOX) layer formed on the Si substrate, and an SOI (Silicon on Insulator) layer, formed on the BOX layer, including an optical element utilizing the SOI layer as a main optical transmission medium. At least part of a waveguide of the optical element includes uniformly distributed and thermally unstable crystal defects.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 2, 2019
    Assignees: NEC CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Tsuyoshi Horikawa, Tohru Mogami, Keizo Kinoshita
  • Publication number: 20190006532
    Abstract: Provided is an optical device in which an Si cap layer is provided on a Ge layer, and which is capable of effectively reducing dark current, while having a good effect on prevention of production line contamination by Ge. One embodiment of the optical device according to the present invention is provided with: a semiconductor layer which contains Ge and has a (001) surface and a facet surface between the (001) surface and a (110) surface; and a cap layer which is formed from Si, and which is formed on the (001) surface and the facet surface of the semiconductor layer. The ratio of the film thickness of the cap layer on the facet surface to the film thickness of the cap layer on the (001) surface is 0.4 or more; and the film thickness of the cap layer on the (001) surface is from 9 nm to 30 nm (inclusive).
    Type: Application
    Filed: July 28, 2016
    Publication date: January 3, 2019
    Applicant: PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shigekazu Okumura, Tohru Mogami, Keizo Kinoshita, Tsuyoshi Horikawa, Junichi Fujikata
  • Patent number: 10162110
    Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: December 25, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Tatsuya Usami, Keiji Sakamoto, Yoshiaki Yamamoto, Shinichi Watanuki, Masaru Wakabayashi, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Publication number: 20180284559
    Abstract: Provided is a silicon-based electro-optic modulator that exhibits an improved carrier plasma effect which is capable of realizing a low current density, low power consumption, a high modulation rate, low-voltage driving and high-speed modulation in a sub-micron region. The electro-optic modulator includes a waveguide structure including an Si or SiGe crystal. The electric field direction of light that propagates inside the waveguide structure is set to be approximately parallel with the <110> direction of the Si or SiGe crystal.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 4, 2018
    Applicants: NEC CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIAT ION
    Inventors: Junichi FUJIKATA, Tohru MOGAMI, Takahiro NAKAMURA, Tsuyoshi HORIKAWA
  • Patent number: 10078182
    Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 18, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shinichi Watanuki, Akira Mitsuiki, Atsuro Inada, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Patent number: 9985149
    Abstract: A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 29, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Publication number: 20180067260
    Abstract: Provided is an optical waveguide circuit avoiding the difficulty of the property compensation based on temperature control, compensated with respect to the property variations due to fabrication error, particularly paid attention in a silicon waveguide, and being low in power consumption and high in performances. The optical waveguide circuit includes a silicon (Si) substrate, a buried oxide film (BOX) layer formed on the Si substrate, and an SOI (Silicon on Insulator) layer, formed on the BOX layer, including an optical element utilizing the SOI layer as a main optical transmission medium. At least part of a waveguide of the optical element includes uniformly distributed and thermally unstable crystal defects.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 8, 2018
    Inventors: Tsuyoshi HORIKAWA, Tohru MOGAMI, Keizo KINOSHITA
  • Publication number: 20170069769
    Abstract: A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.
    Type: Application
    Filed: August 23, 2016
    Publication date: March 9, 2017
    Inventors: Tatsuya USAMI, Yoshiaki YAMAMOTO, Keiji SAKAMOTO, Tohru MOGAMI, Tsuyoshi HORIKAWA, Keizo KINOSHITA
  • Publication number: 20170068047
    Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.
    Type: Application
    Filed: August 22, 2016
    Publication date: March 9, 2017
    Inventors: TATSUYA USAMI, KEIJI SAKAMOTO, YOSHIAKI YAMAMOTO, SHINICHI WATANUKI, MASARU WAKABAYASHI, TOHRU MOGAMI, TSUYOSHI HORIKAWA, KEIZO KINOSHITA
  • Publication number: 20170068051
    Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.
    Type: Application
    Filed: August 22, 2016
    Publication date: March 9, 2017
    Inventors: Shinichi WATANUKI, Akira MITSUIKl, Atsuro INADA, Tohru MOGAMI, Tsuyoshi HORIKAWA, Keizo KINOSHITA
  • Patent number: 6933569
    Abstract: A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: August 23, 2005
    Assignee: NEC Corporation
    Inventors: Risho Koh, Shigeharu Yamagami, Jong-wook Lee, Hitoshi Wakabayashi, Yukishige Saito, Atsushi Ogura, Mitsuru Narihiro, Kohichi Arai, Hisashi Takemura, Tohru Mogami, Toyoji Yamamoto, Yukinori Ochiai
  • Publication number: 20040129975
    Abstract: A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.
    Type: Application
    Filed: September 24, 2003
    Publication date: July 8, 2004
    Applicant: NEC CORPORATION
    Inventors: Risho Koh, Shigeharu Yamagami, Jong-wook Lee, Hitoshi Wakabayashi, Yukishige Saito, Atsushi Ogura, Mitsuru Narihiro, Kohichi Arai, Hisashi Takemura, Tohru Mogami, Toyoji Yamamoto, Yukinori Ochiai
  • Patent number: 6515511
    Abstract: A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The logic gate portion has a MOS transistor. The wire selection portion has a thin-film transistor serving as a transfer gate. The wire selection portion is placed over the logic gate portion via an interlayer insulating film.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: February 4, 2003
    Assignee: NEC Corporation
    Inventors: Tadahiko Sugibayashi, Tohru Mogami
  • Publication number: 20020153573
    Abstract: A gate electrode film of an MIS field effect transistor is formed to have a layered structure composed of conductor films, and so as to have a lower conductor film in contact with a gate insulation film approximately thin enough for at least allowing an upper layer conductor film to displace a potential of a substrate channel region and have a lower layer conductor film of one gate electrode film and a lower layer conductor film of the other gate electrode film of different electric polarity differ in film thickness from each other.
    Type: Application
    Filed: February 22, 2000
    Publication date: October 24, 2002
    Inventor: Tohru Mogami
  • Patent number: 6459126
    Abstract: A MIS transistor has a gate insulating film made of silicon oxynitride and having a specific dielectric constant which is larger than the expected specific dielectric constant calculated based on a weighted average of the specific dielectric constants based on the weight ratio of the silicon oxide and the silicon nitride contained in the silicon oxynitride film. The gate insulating film having a smaller thickness prevents impurities in the overlying gate electrode from penetrating through the gate insulating film to degrade the silicon substrate.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: October 1, 2002
    Assignee: NEC Corporation
    Inventors: Tohru Mogami, Mitsuhiro Togo, Koji Watanabe, Toyoji Yamamoto, Nobuyuki Ikarashi, Kazutoshi Shiba, Toru Tatsumi, Haruhiko Ono
  • Publication number: 20020096721
    Abstract: A MIS transistor has a gate insulating film made of silicon oxynitride and having a specific dielectric constant which is larger than the expected specific dielectric constant calculated based on a weighted average of the specific dielectric constants based on the weight ratio of the silicon oxide and the silicon nitride contained in the silicon oxynitride film. The gate insulating film having a smaller thickness prevents impurities in the overlying gate electrode from penetrating through the gate insulating film to degrade the silicon substrate.
    Type: Application
    Filed: May 11, 2001
    Publication date: July 25, 2002
    Applicant: NEC CORPORATION
    Inventors: Tohru Mogami, Mitsuhiro Togo, Koji Watanabe, Toyoji Yamamoto, Nobuyuki Ikarashi, Kazutoshi Shiba, Toru Tatsumi, Haruhiko Ono
  • Publication number: 20010015450
    Abstract: A semiconductor integrated circuit device has a plurality of basic cells. The basic cells are placed in a matrix form, and are formed on a semiconductor substrate. Each of the basic cells includes a wire selection portion and a logic gate portion. The logic gate portion has a MOS transistor. The wire selection portion has a thin-film transistor serving as a transfer gate. The wire selection portion is placed over the logic gate portion via an interlayer insulating film.
    Type: Application
    Filed: February 16, 2001
    Publication date: August 23, 2001
    Inventors: Tadahiko Sugibayashi, Tohru Mogami
  • Patent number: 5656519
    Abstract: In a method for manufacturing a salicide MOS device, a gate insulating layer and a polycrystalline silicon gate electrode layer are formed on a monocrystalline silicon substrate. A sidewall insulating layer is formed on a sidewall of the gate electrode layer, and impurities are introduced into the substrate with a mask of the sidewall insulating layer and the gate electrode layer, thus forming impurity diffusion regions in the substrate. Then, an upper portion of the gate electrode layer is etched out. Finally, a metal layer is formed on the entire surface, and a heating operation is carried out, so that metal silicide layers are formed on upper portions of the gate electrodes and the impurity diffusion regions. In an alternative embodiment, the gate further comprises an intervening metal nitride layer.
    Type: Grant
    Filed: February 13, 1996
    Date of Patent: August 12, 1997
    Assignee: NEC Corporation
    Inventor: Tohru Mogami
  • Patent number: 5593923
    Abstract: A method of producing a semiconductor device having a refractory metal silicide film includes the steps of implanting ions such as silicon into an active region such as drain/source region to form a damage portion therein, depositing a refractory metal on the damage portion, and annealing to form the refractory metal silicide layer. This silicide layer is formed by the refractory metal being reacted with silicon in the damage portion of the active region.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: January 14, 1997
    Assignee: NEC Corporation
    Inventors: Tadahiko Horiuchi, Takashi Ishigami, Hiroyuki Nakamura, Tohru Mogami, Hitoshi Wakabayashi, Takemitsu Kunio, Koichiro Okumura