Patents by Inventor Tohru Nomura

Tohru Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9087924
    Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: July 21, 2015
    Assignee: DENSO CORPORATION
    Inventors: Tetsuto Yamagishi, Tohru Nomura, Norihisa Imaizumi, Yasutomi Asai
  • Publication number: 20140217620
    Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.
    Type: Application
    Filed: April 9, 2014
    Publication date: August 7, 2014
    Applicant: DENSO CORPORATION
    Inventors: Tetsuto YAMAGISHI, Tohru NOMURA, Norihisa IMAIZUMI, Yasutomi ASAI
  • Patent number: 8749055
    Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: June 10, 2014
    Assignee: DENSO CORPORATION
    Inventors: Tetsuto Yamagishi, Tohru Nomura, Norihisa Imaizumi, Yasutomi Asai
  • Publication number: 20120223444
    Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.
    Type: Application
    Filed: April 18, 2012
    Publication date: September 6, 2012
    Applicant: DENSO CORPORATION
    Inventors: Tetsuto YAMAGISHI, Tohru Nomura, Norihisa Imaizumi, Yasutomi Asai
  • Patent number: 8207607
    Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: June 26, 2012
    Assignee: DENSO CORPORATION
    Inventors: Tetsuto Yamagishi, Tohru Nomura, Norihisa Imaizumi, Yasutomi Asai
  • Patent number: 7675150
    Abstract: An electric circuit device and related manufacturing method are disclosed as having a case incorporating therein a substrate on which electric circuit elements are mounted. A sealant is filled in the case to cover the electric circuit elements and the substrate and is composed of a lower layer gel and an upper layer gel formed in a two-layer structure. The upper layer gel has a penetration equal to or less than 90 and the lower layer gel has a penetration greater than that of the upper layer gel to allow the upper layer gel to suppress vibration of a surface of the lower gel for thereby suppressing the deformation of the lower layer gel even in the presence of a tendency causing the electric circuit elements or the substrate to vibrate, preventing a degraded function in insulation, waterproof and vibrational relaxation of the lower layer gel.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: March 9, 2010
    Assignee: Denso Corporation
    Inventor: Tohru Nomura
  • Publication number: 20090152714
    Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.
    Type: Application
    Filed: December 9, 2008
    Publication date: June 18, 2009
    Applicant: DENSO CORPORATION
    Inventors: Tetsuto Yamagishi, Tohru Nomura, Norihisa Imaizumi, Yasutomi Asai
  • Patent number: 7417318
    Abstract: A thick film circuit board that can be produced at a low cost, a method of producing the same, and an integrated circuit device. A first thick film circuit board has conducting layers of a copper-containing conductor fired at not higher than 750° C., and includes conducting portions formed by using a silver-containing conductor. A second thick film circuit board has conductors that are formed in the through holes so as to close the openings of at least the one side thereof. The thick film circuit board is produced at a low cost and suppresses a drop in electric conductivity when it is in use.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: August 26, 2008
    Assignee: Denso Corporation
    Inventors: Tohru Nomura, Yoshihiro Shimoide, Yoshihiko Shiraishi, Rikiya Kamimura, Hiroshi Kasugai
  • Publication number: 20070278623
    Abstract: An electric circuit device and related manufacturing method are disclosed as having a case incorporating therein a substrate on which electric circuit elements are mounted. A sealant is filled in the case to cover the electric circuit elements and the substrate and is composed of a lower layer gel and an upper layer gel formed in a two-layer structure. The upper layer gel has a penetration equal to or less than 90 and the lower layer gel has a penetration greater than that of the upper layer gel to allow the upper layer gel to suppress vibration of a surface of the lower gel for thereby suppressing the deformation of the lower layer gel even in the presence of a tendency causing the electric circuit elements or the substrate to vibrate, preventing a degraded function in insulation, waterproof and vibrational relaxation of the lower layer gel.
    Type: Application
    Filed: June 1, 2007
    Publication date: December 6, 2007
    Applicant: DENSO CORPORATION
    Inventor: Tohru Nomura
  • Publication number: 20040212085
    Abstract: A thick film circuit board that can be produced at a low cost, a method of producing the same, and an integrated circuit device. A first thick film circuit board has conducting layers of a copper-containing conductor fired at not higher than 750° C., and includes conducting portions formed by using a silver-containing conductor. A second thick film circuit board has conductors that are formed in the through holes so as to close the openings of at least the one side thereof. The thick film circuit board is produced at a low cost and suppresses a drop in electric conductivity when it is in use.
    Type: Application
    Filed: April 26, 2004
    Publication date: October 28, 2004
    Applicant: DENSO CORPORATION
    Inventors: Tohru Nomura, Yoshihiro Shimoide, Yoshihiko Shiraishi, Rikiya Kamimura, Hiroshi Kasugai
  • Patent number: 6565812
    Abstract: A base is provided with a concave and three leads, and the central lead is bent to the side opposite to the concave, and the other leads are bent to the side of the concave. A central electrode of a sensor element is attached to the central lead and the bottom of the concave and a coil serving as both a heater and an electrode is attached to the other leads to support the sensor element on a small base at four points.
    Type: Grant
    Filed: November 1, 2000
    Date of Patent: May 20, 2003
    Assignee: Figaro Engineering Inc.
    Inventors: Tohru Nomura, Hideki Okoshi, Tomoko Yoshimura, Yutaka Kishimoto, Yuichiro Tajiri
  • Patent number: 6499335
    Abstract: A central electrode 12 is arranged in a coiled heater electrode 10. They are buried in a SnO2-based inner area 6, and the entirety is covered by a filter 8. The volume of the inner area 6 is set at from 1×10−3 mm3 to 16×10−3 mm3, the total volume of the bead 4 is set at from 15×10−3 mm3 to 70×10−3 mm3, and the ratio of the total volume of the bead 4 to the volume of the inner area 6 is set at from four to twenty to bring the sensor resistance in CO and that in methane closer to each other and increase the selectivity from hydrogen.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: December 31, 2002
    Assignee: Figaro Engineering, Inc.
    Inventors: Tohru Nomura, Hideki Okoshi, Tomoko Yoshimura
  • Publication number: 20010003916
    Abstract: A central electrode 12 is arranged in a coiled heater electrode 10. They are buried in a SnO2-based inner area 6, and the entirety is covered by a filter 8. The volume of the inner area 6 is set at from 1×10−3 mm3 to 16×10−3 mm3, the total volume of the bead 4 is set at from 15×10−3 mm3 to 70×10−3 mm3, and the ratio of the total volume of the bead 4 to the volume of the inner area 6 is set at from 4 to 20 to bring the sensor resistance in CO and that in methane closer to each other and increase the selectivity from hydrogen.
    Type: Application
    Filed: December 13, 2000
    Publication date: June 21, 2001
    Applicant: Figaro Engineering, Inc.
    Inventors: Tohru Nomura, Hideki Okoshi, Tomoko Yoshimura
  • Patent number: 5729893
    Abstract: A method for producing a multilayer ceramic circuit substrate having therein internal conductor patterns comprising W and/or Mo as a main component and surface conductor patterns comprising Cu as a main component formed onto a surface layer of the multilayer ceramic circuit substrate, wherein an intermediate metal layer comprising 40 to 90 wt. % of W and/or Mo and 10 to 60 wt. % of at least one element selected from the group consisting of Ir, Pt, Ti, and Cr is formed in through-holes of the surface layer and on parts of the surface layer in the vicinity of the through holes on the surface layer, whereby the internal conductor patterns and the surface conductor patterns are electrically connected through the intermediate metal layer. The alumina multilayer ceramic circuit substrate enables an excellent bonding strength and electrical conductivity between the internal conductors and the surface conductors and high precision wiring and miniaturization of an electronic circuit part.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: March 24, 1998
    Assignee: Sumitomo Metal (SMI) Electronics Devices, Inc.
    Inventors: Nozomi Tanifuji, Akihiko Naito, Koji Sawada, Tohru Nomura, Yoshiyuki Miyase, Takashi Nagasaka
  • Patent number: 5709927
    Abstract: A thick film circuit board comprising an insulating substrate; conductor wiring layers of a conductive material containing an oxide and formed on the insulating substrate by printing and firing; a resistance layer of a resistive material having a selected sheet resistance, being chemically reactive with the oxide, and formed between and bridging the conductor wiring layers by printing and firing; and a conductive barrier layer interposed between each of the conductor wiring layers and the resistance layer to prevent chemical reaction between the oxide of the conductor wiring layers and the resistive material of the resistance layer.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: January 20, 1998
    Assignees: Nippondenso Co., Ltd., Sumitomo Metal Ceramics Inc.
    Inventors: Yoshiyuki Miyase, Tohru Nomura, Akihiko Naito, Takamasa Okumura
  • Patent number: 5627344
    Abstract: A multilayer ceramic circuit substrate having therein internal conductor patterns comprising W and/or Mo as a main component and surface conductor patterns comprising Cu as a main component formed onto a surface layer of the multilayer ceramic circuit substrate, wherein an intermediate metal layer comprising 40 to 90 wt. % of W and/or Mo and 10 to 60 wt. % of at least one element selected from the group consisting of Ir, Pt, Ti, and Cr is formed in through-holes of the surface layer and on parts of the surface layer in the vicinity of the through holes on the surface layer, whereby the internal conductor patterns and the surface conductor patterns are electrically connected through the intermediate metal layer. The alumina multilayer ceramic circuit substrate provides an excellent bonding strength and electrical conductivity between the internal conductors and the surface conductors and enables high precision wiring and miniaturization of an electronic circuit part.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: May 6, 1997
    Assignees: Sumitomo Metal Ceramics Inc., Nippondenso Co., Ltd.
    Inventors: Nozomi Tanifuji, Akihiko Naito, Koji Sawada, Tohru Nomura, Yoshiyuki Miyase, Takashi Nagasaka
  • Patent number: 5156903
    Abstract: A multilayer ceramic substrate having improved mechanical and electrical properties and suitable for use to form a hybrid integrated circuit and a process for the manufacture thereof. The multilayer ceramic substrate has at least one layer of a first conductor based on a refractory metal as an internal conductor layer and at least one layer of a Cu-based second conductor as a surface conductor layer, wherein the second conductor layer is connected to the first conductor layer through a metallic layer formed by coating with a metalloorganics paste containing one or more metals selected from the group consisting of Pt, Pd, Ni, Cu, Au, Rh, Ru, Re, Co, and Ir followed by firing in an inert or reducing atmosphere.
    Type: Grant
    Filed: December 21, 1990
    Date of Patent: October 20, 1992
    Assignees: Sumitomo Metal Ceramics Inc., Nippon Denso Co., Ltd.
    Inventors: Takamasa Okumura, Kohmei Kawaguchi, Masataka Aoki, Takashi Nagasaka, Tohru Nomura, Yoshiyuki Miyase
  • Patent number: 4994880
    Abstract: Base regions of first and second stage transistors are formed in a semiconductor substrate consisting of low and high resistivity collector layers, and emitter regions are formed in the respective base regions. The emitter region of the second stage transistor has an interdigital structure with a plurality of finger portions, and an emitter surface electrode is formed on the emitter region of the second stage transistor. The second stage transistor emitter surface electrode has an extending portion at a position spaced apart from a transistor operation region where the finger portions are formed. An emitter connection electrode is formed on the extending portion, and a lead is connected by soldering or the like to the emitter connection electrode.
    Type: Grant
    Filed: September 25, 1989
    Date of Patent: February 19, 1991
    Assignee: Nippondenso Co., Ltd.
    Inventors: Naohito Kato, Yoshiyuki Miyase, Tomoatsu Makino, Kasuhiro Yamada, Masami Yamaoka, Takeshi Matsui, Masahiro Yamamoto, Yoshiki Ishida, Tohru Nomura