Patents by Inventor Tohru Ohsaka

Tohru Ohsaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9084364
    Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: July 14, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai, Tohru Ohsaka
  • Publication number: 20130343024
    Abstract: On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 26, 2013
    Inventors: Sou Hoshi, Nobuaki Yamashita, Yusuke Murai, Tohru Ohsaka
  • Patent number: 7851900
    Abstract: In a stacked semiconductor package, since electric power is supplied to a second semiconductor package through a first semiconductor package, a power supply path becomes complicated and fluctuation of its inductance becomes large, whereby power bounce occurs to reduce signal quality and also prevent high speed signal communication. Therefore, according to the present invention, a first solder ball group for joint to a printed wiring board is attached to a second layer of the first semiconductor package, and a second solder ball group for joint to the first semiconductor package and a solder group for power supply for direct joint to the printed wiring board are provided on the second layer of the second semiconductor package, whereby electric power can be directly supplied from the printed wiring board.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: December 14, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tohru Ohsaka, Hiroshi Kondo
  • Patent number: 7839652
    Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: November 23, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tohru Ohsaka
  • Patent number: 7594105
    Abstract: This invention effectively prevents potential fluctuation in the power supply terminal of a semiconductor device, that is, noise from flowing out to a main power supply wiring. A multilayer print circuit board includes a first power supply via hole which connects to the power supply terminal of a semiconductor integrated circuit on a first surface layer and extends from the first surface layer to a second surface layer, a ground via hole which connects to a ground conductive layer, extends from the ground conductive layer to the second surface layer, and connects to the first power supply via hole on the second surface layer through a bypass capacitor, a first clearance hole which is formed in a power supply conductive layer, and a second clearance hole which is formed in the ground conductive layer. The first clearance hole is larger than the second clearance hole.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: September 22, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tohru Ohsaka
  • Publication number: 20090051015
    Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.
    Type: Application
    Filed: October 22, 2008
    Publication date: February 26, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Tohru Ohsaka
  • Patent number: 7495928
    Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: February 24, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tohru Ohsaka
  • Publication number: 20080128873
    Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 5, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Tohru Ohsaka
  • Patent number: 7349224
    Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: March 25, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tohru Ohsaka
  • Patent number: 7277298
    Abstract: According to the invention, even when high-speed differential signal pins are arranged on the inner side of a BGA, they can be wired on a printed wiring board at a low cost. In a multi-terminal device (1) having one surface where a large number of connection terminals are arrayed planarly, terminals (3) that need not be electrically connected individually are arranged between differential signal terminals (2) of the multi-terminal device and the periphery of the multi-terminal device.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: October 2, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tohru Ohsaka
  • Publication number: 20070136618
    Abstract: This invention effectively prevents potential fluctuation in the power supply terminal of a semiconductor device, that is, noise from flowing out to a main power supply wiring. A multilayer print circuit board includes a first power supply via hole which connects to the power supply terminal of a semiconductor integrated circuit on a first surface layer and extends from the first surface layer to a second surface layer, a ground via hole which connects to a ground conductive layer, extends from the ground conductive layer to the second surface layer, and connects to the first power supply via hole on the second surface layer through a bypass capacitor, a first clearance hole which is formed in a power supply conductive layer, and a second clearance hole which is formed in the ground conductive layer. The first clearance hole is larger than the second clearance hole.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 14, 2007
    Inventor: Tohru Ohsaka
  • Patent number: 7199308
    Abstract: A multi-layered printed wiring board, capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises, has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, the wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: April 3, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tohru Ohsaka
  • Publication number: 20060208348
    Abstract: In a stacked semiconductor package, since electric power is supplied to a second semiconductor package through a first semiconductor package, a power supply path becomes complicated and fluctuation of its inductance becomes large, whereby power bounce occurs to reduce signal quality and also prevent high speed signal communication. Therefore, according to the present invention, a first solder ball group for joint to a printed wiring board is attached to a second layer of the first semiconductor package, and a second solder ball group for joint to the first semiconductor package and a solder group for power supply for direct joint to the printed wiring board are provided on the second layer of the second semiconductor package, whereby electric power can be directly supplied from the printed wiring board.
    Type: Application
    Filed: March 17, 2006
    Publication date: September 21, 2006
    Inventors: Tohru Ohsaka, Hiroshi Kondo
  • Publication number: 20060065965
    Abstract: According to the invention, even when high-speed differential signal pins are arranged on the inner side of a BGA, they can be wired on a printed wiring board at a low cost. In a multi-terminal device (1) having one surface where a large number of connection terminals are arrayed planarly, terminals (3) that need not be electrically connected individually are arranged between differential signal terminals (2) of the multi-terminal device and the periphery of the multi-terminal device.
    Type: Application
    Filed: September 27, 2005
    Publication date: March 30, 2006
    Inventor: Tohru Ohsaka
  • Publication number: 20050230823
    Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 20, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Tohru Ohsaka
  • Publication number: 20050039947
    Abstract: A multi-layered printed wiring board is provided that is capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.
    Type: Application
    Filed: September 27, 2004
    Publication date: February 24, 2005
    Applicant: Canon Kabushiki Kaisha
    Inventor: Tohru Ohsaka
  • Patent number: 6800814
    Abstract: A multi-layered printed wiring board capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: October 5, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tohru Ohsaka
  • Publication number: 20020108779
    Abstract: A multi-layered printed wiring board is provided that is capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.
    Type: Application
    Filed: January 16, 2002
    Publication date: August 15, 2002
    Inventor: Tohru Ohsaka
  • Patent number: 6335866
    Abstract: A printed wiring board unit for use with an electronic apparatus in which the unit is formed by a power circuit and a digital circuit. The power circuit is constructed as a power circuit board made of a single-sided board, and the digital circuit is a high density digital circuit board which is smaller than the power circuit board. The digital circuit board is formed into a module by mounting thereon an IC, etc., which operates at the highest internal clock frequency. This reduced digital circuit board is mounted onto the power circuit board with spacing between parts in a layered structure, thereby improving unwanted radiation noise characteristics without increasing costs.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: January 1, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tohru Ohtaki, Tohru Ohsaka
  • Patent number: 5973929
    Abstract: A circuit board having a printed capacitor whose capacitance is easily adjusted includes a plurality of through-holes arranged in arrays and electrically connected to each other via conductive films. Therefore, first and second electrode portions are arranged to oppose each other, and form a printed capacitor. The capacitance of the capacitor can be adjusted by the number and diameter of through-holes, and the interval between each two adjacent through-holes. Therefore, even when a large-capacitance capacitor is to be formed, the printed capacitor can be rendered compact.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: October 26, 1999
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tomoyasu Arakawa, Toru Otaki, Yasushi Takeuchi, Hideho Inagawa, Yoshimi Terayama, Tohru Ohsaka