Patents by Inventor Tohru Oka

Tohru Oka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10879349
    Abstract: A method for manufacturing a semiconductor device having a edge termination region comprises a stacking process, an ion implantation process, and a heat treatment process. In the stacking process, a p-type semiconductor layer containing a p-type impurity is stacked on an n-type semiconductor layer containing an n-type impurity. In the ion implantation process, at least one of the n-type impurity and the p-type impurity is ion-implanted into the p-type semiconductor layer located in the edge termination region. The ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a p-type impurity containing region in at least part of the n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 29, 2020
    Assignee: TOYODA GOSET CO., LTD.
    Inventors: Tohru Oka, Nariaki Tanaka, Junya Nishii
  • Patent number: 10490408
    Abstract: A method for manufacturing a semiconductor device comprises: a stacking process that stacks a p-type semiconductor layer of Group III nitride containing a p-type impurity on a first n-type semiconductor layer of Group III nitride containing an n-type impurity; a p-type ion implantation process that ion-implants the p-type impurity into the p-type semiconductor layer; and a heat treatment process that performs heat treatment to activate the ion-implanted p-type impurity. The p-type ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a first p-type impurity containing region in at least part of the first n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: November 26, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Junya Nishii, Tohru Oka, Nariaki Tanaka
  • Patent number: 10468515
    Abstract: There is provided a semiconductor device comprising a substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a trench and an insulating film arranged to cover a surface of the trench. The first semiconductor layer has a carrier concentration that provides a peak in a thickness direction perpendicular to a plane direction. A high carrier concentration area having a peak of the carrier concentration in the first semiconductor layer is extended in the plane direction at a location away from the trench to be located on the substrate side of the trench. This configuration reduces the on resistance while suppressing reduction of the breakdown voltage in the semiconductor device.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: November 5, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Tsutomu Ina, Tohru Oka
  • Patent number: 10403727
    Abstract: To provide a technique for alleviating electric field concentration at an end portion and the vicinity of the end portion of the bottom surface of a trench. In a non-active region, a semiconductor device comprises: an outer trench penetrating a third semiconductor layer and a second semiconductor layer to reach a first semiconductor layer, and surrounding an active region; a second insulating film covering the surface of the outer trench; a conductor formed in the outer trench covered by the second insulating film and electrically insulated from a control electrode and a contact electrode; and an outer electrode located outside the outer trench, contacting the second semiconductor layer, and being electrically connected to the contact electrode.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 3, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Tsutomu Ina, Yukihisa Ueno, Tohru Oka
  • Patent number: 10332754
    Abstract: There is provided a method of manufacturing a nitride semiconductor device. The method of manufacturing the nitride semiconductor device comprises: a first film forming process that forms a first film on a nitride semiconductor layer; an ion implantation process that implants a P-type impurity into the nitride semiconductor layer through the first film by ion implantation; a second film forming process that forms a second film on the first film, after the ion implantation process; and a heat treatment process that processes the nitride semiconductor layer by heat treatment after the second film forming process. This suppresses the surface of the nitride semiconductor layer from being roughened.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: June 25, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takaki Niwa, Takahiro Fujii, Masayoshi Kosaki, Tohru Oka
  • Patent number: 10276731
    Abstract: A Schottky barrier diode comprises a semiconductor layer configured to include a surface and a plurality of recesses that are recessed relative to the surface; and a Schottky electrode arranged to form a Schottky contact with the surface. When the semiconductor layer is viewed from a surface side thereof, the surface is arranged continuously, and distances on the surface between adjacent recesses are substantially identical. This configuration suppresses a photoresist from being left in any unintended portion.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 30, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Kazuya Hasegawa, Tohru Oka
  • Patent number: 10256323
    Abstract: A technique of improving the breakdown voltage of a semiconductor device is provided. There is provided a method of manufacturing a semiconductor device comprising a process of forming a p-type semiconductor layer that contains a p-type impurity and has a dislocation density of not higher than 1.0×107 cm?2, on an n-type semiconductor layer that contains an n-type impurity and has a dislocation density of not higher than 1.0×107 cm?2; an n-type semiconductor region forming process of forming an n-type semiconductor region in at least part of the p-type semiconductor layer by ion-implanting an n-type impurity into the p-type semiconductor layer and performing heat treatment to activate the ion-implanted n-type impurity; and a process of forming a trench that is recessed to pass through the p-type semiconductor layer and reach the n-type semiconductor layer.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 9, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Nariaki Tanaka, Tohru Oka
  • Publication number: 20190097004
    Abstract: To provide a technique for alleviating electric field concentration at an end portion and the vicinity of the end portion of the bottom surface of a trench. In a non-active region, a semiconductor device comprises: an outer trench penetrating a third semiconductor layer and a second semiconductor layer to reach a first semiconductor layer, and surrounding an active region; a second insulating film covering the surface of the outer trench; a conductor formed in the outer trench covered by the second insulating film and electrically insulated from a control electrode and a contact electrode; and an outer electrode located outside the outer trench, contacting the second semiconductor layer, and being electrically connected to the contact electrode.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 28, 2019
    Inventors: Tsutomu INA, Yukihisa UENO, Tohru OKA
  • Patent number: 10236373
    Abstract: To suppress current leakage in a semiconductor device having a gate insulating film and a gate electrode. A gate electrode is continuously formed in a film via a gate insulating film on the bottom surface of a trench, the side surfaces of a trench, and the top surfaces of a second n-type layer in the vicinity of the side surfaces of the trench. The ends of the bottom surface of the gate electrode are aligned with the ends of the top surface of the gate insulating film, and the ends of the bottom surface of the gate insulating film are formed in contact with the surfaces of the second n-type layer facing the ends of the bottom surface of the gate electrode. The passivation film covers the entire top surface of the device except the contact holes of the gate electrode and the source electrode.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: March 19, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Junichiro Kurosaki, Tohru Oka, Junya Nishii, Tsutomu Ina
  • Patent number: 10177234
    Abstract: A semiconductor device having a trench gate structure is configured to include a first n-type semiconductor layer, a p-type semiconductor layer, a trench, an insulating film, a gate electrode, a source electrode and a drain electrode. The first n-type semiconductor layer includes a p-type impurity-containing region configured to contain a p-type impurity at a higher concentration than an n-type impurity. The p-type impurity-containing region is arranged to adjoin the p-type semiconductor layer. In a stacking direction of the first n-type semiconductor layer and the p-type semiconductor layer, the p-type impurity-containing region is provided at a position that does not at least partly overlap with the source electrode and that overlaps with an outer periphery of a bottom face of the trench. This configuration suppresses an increase in capacity between the drain and the source, while improving the breakdown voltage of the semiconductor device.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 8, 2019
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Nariaki Tanaka, Tohru Oka
  • Patent number: 10153356
    Abstract: A technique of suppressing the potential crowding in the vicinity of the outer periphery of a bottom face of a trench without ion implantation of a p-type impurity is provided. A method of manufacturing a semiconductor device having a trench gate structure comprises an n-type semiconductor region forming process. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which a p-type impurity contained in a p-type semiconductor layer is diffused is formed in at least part of an n-type semiconductor layer that is located below an n-type semiconductor region.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: December 11, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Tohru Oka, Nariaki Tanaka
  • Patent number: 10153352
    Abstract: A technique of reducing the complication in manufacture is provided. There is provided a semiconductor device comprising an n-type semiconductor region made of a nitride semiconductor containing gallium; a p-type semiconductor region arranged to be adjacent to and in contact with the n-type semiconductor region and made of the nitride semiconductor; a first electrode arranged to be in ohmic contact with the n-type semiconductor region; and a second electrode arranged to be in ohmic contact with the p-type semiconductor region. The first electrode and the second electrode are mainly made of one identical metal. The identical metal is at least one metal selected from the group consisting of palladium, nickel and platinum. A concentration of a p-type impurity in the n-type semiconductor region is approximately equal to a concentration of the p-type impurity in the p-type semiconductor region.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: December 11, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Nariaki Tanaka, Tohru Oka
  • Publication number: 20180286945
    Abstract: A method for manufacturing a semiconductor device having a edge termination region comprises a stacking process, an ion implantation process, and a heat treatment process. In the stacking process, a p-type semiconductor layer containing a p-type impurity is stacked on an n-type semiconductor layer containing an n-type impurity. In the ion implantation process, at least one of the n-type impurity and the p-type impurity is ion-implanted into the p-type semiconductor layer located in the edge termination region. The ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a p-type impurity containing region in at least part of the n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.
    Type: Application
    Filed: March 13, 2018
    Publication date: October 4, 2018
    Inventors: Tohru Oka, Nariaki Tanaka, Junya Nishii
  • Publication number: 20180286685
    Abstract: A method for manufacturing a semiconductor device comprises: a stacking process that stacks a p-type semiconductor layer of Group III nitride containing a p-type impurity on a first n-type semiconductor layer of Group III nitride containing an n-type impurity; a p-type ion implantation process that ion-implants the p-type impurity into the p-type semiconductor layer; and a heat treatment process that performs heat treatment to activate the ion-implanted p-type impurity. The p-type ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a first p-type impurity containing region in at least part of the first n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.
    Type: Application
    Filed: March 8, 2018
    Publication date: October 4, 2018
    Inventors: Junya NISHII, Tohru OKA, Nariaki TANAKA
  • Publication number: 20180269335
    Abstract: A Schottky barrier diode comprises a semiconductor layer configured to include a surface and a plurality of recesses that are recessed relative to the surface; and a Schottky electrode arranged to form a Schottky contact with the surface. When the semiconductor layer is viewed from a surface side thereof, the surface is arranged continuously, and distances on the surface between adjacent recesses are substantially identical. This configuration suppresses a photoresist from being left in any unintended portion.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 20, 2018
    Inventors: Kazuya HASEGAWA, Tohru Oka
  • Publication number: 20180261673
    Abstract: A semiconductor device having a trench gate structure is configured to include a first n-type semiconductor layer, a p-type semiconductor layer, a trench, an insulating film, a gate electrode, a source electrode and a drain electrode. The first n-type semiconductor layer includes a p-type impurity-containing region configured to contain a p-type impurity at a higher concentration than an n-type impurity. The p-type impurity-containing region is arranged to adjoin the p-type semiconductor layer. In a stacking direction of the first n-type semiconductor layer and the p-type semiconductor layer, the p-type impurity-containing region is provided at a position that does not at least partly overlap with the source electrode and that overlaps with an outer periphery of a bottom face of the trench. This configuration suppresses an increase in capacity between the drain and the source, while improving the breakdown voltage of the semiconductor device.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 13, 2018
    Inventors: Nariaki TANAKA, Tohru Oka
  • Patent number: 10026851
    Abstract: There is provided an MPS diode comprising a first semiconductor layer that is an N type; P-type semiconductor regions and N-type semiconductor regions that are arranged alternately on one surface of the first semiconductor layer; and a Schottky electrode that is in Schottky junction with the N-type semiconductor regions and is arranged to be adjacent to and in contact with at least part of the P-type semiconductor regions. A donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the first semiconductor layer is lower than the donor concentration in an area of the first semiconductor layer that is adjacent to and in contact with the N-type semiconductor region and is lower than the donor concentration in an area of the N-type semiconductor region that is adjacent to and in contact with the Schottky electrode. This configuration improves a breakdown voltage under applying a reverse bias voltage and reduces a rising voltage under applying a forward bias voltage.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 17, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Takaki Niwa, Takahiro Fujii, Masayoshi Kosaki, Tohru Oka
  • Patent number: 10026808
    Abstract: A semiconductor device includes a substrate, a semiconductor layer that is formed on the substrate and includes a pn junction or a hetero-junction, an insulating film that is formed on the semiconductor layer to be in contact with an end of the pn junction or an end of the hetero-junction, and an electrode formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: July 17, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Tohru Oka, Kazuya Hasegawa, Noriaki Murakami, Takahiro Sonoyama, Nariaki Tanaka
  • Patent number: 9972725
    Abstract: There is provided a semiconductor device configured to include a plurality of semiconductor units formed in a semiconductor layer. Each of the semiconductor units comprises a mesa portion; a Schottky electrode formed on the mesa portion; an insulating film formed continuously on another portion of the Schottky electrode that is nearer to an edge of an upper face of the mesa portion than one portion of the Schottky electrode, on a side face of the mesa portion, and on a surface of the semiconductor layer other than the mesa portion; and a wiring electrode formed on the Schottky electrode and the insulating film. An angle between the side face of the mesa portion and the surface of the semiconductor layer is 90 degrees. A part of the wiring electrode is placed between the insulating films formed on opposed side faces of adjacent mesa portions.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 15, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Kazuya Hasegawa, Tohru Oka, Nariaki Tanaka
  • Publication number: 20180069135
    Abstract: There is provided a semiconductor device configured to include a plurality of semiconductor units formed in a semiconductor layer. Each of the semiconductor units comprises a mesa portion; a Schottky electrode formed on the mesa portion; an insulating film formed continuously on another portion of the Schottky electrode that is nearer to an edge of an upper face of the mesa portion than one portion of the Schottky electrode, on a side face of the mesa portion, and on a surface of the semiconductor layer other than the mesa portion; and a wiring electrode formed on the Schottky electrode and the insulating film. An angle between the side face of the mesa portion and the surface of the semiconductor layer is 90 degrees. A part of the wiring electrode is placed between the insulating films formed on opposed side faces of adjacent mesa portions.
    Type: Application
    Filed: July 28, 2017
    Publication date: March 8, 2018
    Inventors: Kazuya HASEGAWA, Tohru OKA, Nariaki TANAKA