Abstract: A semiconductor memory device includes a memory cell which has a transistor and a ferroelectric capacitor, the transistor having a source-drain path and a gate connected to a word line, the capacitor being connected at a first end to a plate line and connected at a second end to a bit line through the source-drain path. A control circuit controls, during a test-mode operation, the memory cell so that a plate-line signal sent through the plate line to the memory cell and a bit-line signal sent through the bit line to the memory cell are set at a same potential.

Abstract: On a semiconductor wafer, there are formed chip areas for storing memory areas, scribe areas for cutting the semiconductor wafer, pads for supplying electric signals from the outside in order to write data into the memory areas, and lead wires for electrically connecting the pads with the memory areas. The pads are formed within the scribe areas. After data has been written into the memory areas through the pads, the semiconductor wafer is cut along the scribe areas, thereby obtaining semiconductor chips. At the time of this cutting, the pads or the lead wires are cut.

Abstract: A semiconductor memory device has a first ferroelectric memory cell in which data is written after the device is mounted on a board, and a second ferroelectric memory cell whose capacitance is larger than that of the first ferroelectric memory cell. This second ferroelectric memory cell is utilized as a memory cell in which cipher or the like are written in the fabrication process. The second ferroelectric memory cell is formed with a combination of a plurality of the first ferroelectric memory cells. In order to realize the second ferroelectric memory cell, word lines or plate lines corresponding to a plurality memory-cell rows may be short-circuited. Alternatively, bit lines corresponding to a plurality memory-cell columns may be short-circuited.

Abstract: A flip-flop includes two gates each having a CMOS circuit and a bipolar circuit. One bipolar circuit related to one of the gates includes first and second bipolar transistors, and the other bipolar circuit includes third and fourth bipolar transistors. A discharge circuit discharges the base of the first bipolar transistor in response to a change in a second input and discharges the base of the third bipolar transistor in response to a first input. The first and second inputs are complementary inputs. A charge cirucit charges the base of the second bipolar transistor in response to the second input and charges the base of the fourth bipolar transistor in response to the first input.

Abstract: A semiconductor memory device provided with at least one block pair. Each block contains therein bit line pairs, word lines, memory cells, and circuitry for writing data by cooperating with the bit line pairs. The wiring pattern of the writing part located in one of the blocks is reversed to that of the writing part located in another block adjacent thereto, whereby the two facing bit lines of different blocks assume opposite logic levels when the same data logic is written into all the memory cells.

Abstract: A semiconductor memory device in which a bipolar memory cell includes two cross-coupled transistors. The collector load is a Schottky barrier diode. A capacitor is formed to be connected to the Schottky barrier diode. The capacitor is formed by a junction between a P.sup.+ -type diffusion region and an N.sup.+ -type buried layer functioning as a collector of the transistor. The P.sup.+ -type diffusion region is formed in the periphery of the Schottky barrier diode and between a metal layer connected to a word line and the N.sup.+ -type buried layer. By the capacitor, the stability of the memory holding state is improved without deteriorating the operating speed of the memory cell.