Abstract: A state tracer system comprising a counter for counting the time taken until, upon receipt of a first request signal from a storage unit, an error takes place; an A-register within which the count number A of this counter is set and its state is held; an X-register which allows the time taken to reach the necessary data to be arbitrarily set; an A-subtracting circuit for subtracting the count number A held by the A-register and the count number X held by the X-register to emit (A - X); a comparator for comparing the output value (A - X) of the A-subtracting circuit and the outpost value of the counter; and means for entering the output (A - X) from the comparator to a stop condition circuit of the tracer memory as a stop signal so that, by setting the count number X of the X-register to several tens to hundreds of micorseconds.

Abstract: A plurality of banks is divided into a plurality of bank groups and a pair of read and write data control registers is assigned to each of the bank groups. A memory main controller is operatively coupled to the bank groups and controls read/write operations of the banks. The memory main controller receives bank access requests from a system controller and generates a request rejected signal in the event that a bank access request consecutively occurs in connection with one bank group. Thus, application of two successive data to each of the read and write data control registers with the same bank group is prohibited, and erroneous data storage in the above-mentioned data control registers is prevented.