Abstract: A plurality of measuring positions on a sample are sequentially irradiated with electron beams having identical cross sectional shapes, currents produced in the sample when the individual measuring positions are irradiated with electron beams are measured and the measured currents or physical amounts derived from the measured currents are displayed on a two-dimensional plane as a function of measuring position.

Abstract: A production managing system for semiconductor devices includes, in a semiconductor producing center C, production devices 11a-11c for producing semiconductor devices, in-line measuring devices 12a-12c for measuring data of a lot, a database 2 storing data of production methods, the measured data, the specifications of the process steps corresponding to the measured data, the estimated yield, the data of lot input date and hour, the data of the scheduled date on which the process step is performed, the data of actual date of completion in every step and the data of the scheduled date of completion of the semiconductor devices of every lot, correspondingly to a lot number data of the semiconductor devices (chips) and a server 1 including an estimated yield operating unit 1a for calculating the estimated yield, which is a final yield, on the basis of the specifications and the measured data, and a production managing unit 1b for performing a production management of semiconductor devices ordered by a user on th

Abstract: A semiconductor wafer is radiated with an electron beam so that the inelastic scattering takes place in the narrow region, and current flows out from the narrow region; the amount of current is dependent on the substance or substances in the narrow region so that the analyst evaluates the degree of contamination on the basis of the substance or substances specified in the narrow region.

Abstract: A semiconductor device inspecting apparatus capable of a high-precision nondestructive inspection with a reduction of external noises, by using a value of an area having no hole as a background value for a correction when measuring an average current, measuring the current in a current differential input amplifier constitution, automatically judging whether a result of the measurement is caused by a defect of the device or of the equipment on the basis of a measured current waveform, measuring a current value of electron beams, and storing and reusing a waiting time between irradiation with electron beams and stabilization of the current measurement value.

Abstract: The present invention provides a semiconductor wafer tester including a substrate, at least one chip mounted on an upper surface of the substrate, the chip having function as a tester, the chip being electrically connected to a contact formed on a lower surface of the substrate through an internal wiring formed in the substrate, and a contact film having at least one first bump formed on an upper surface thereof and at least one second bump formed on a lower surface thereof, the first bump being electrically connected to the second bump through an internal wiring formed throughout the contact film, the contact film being to be disposed to be sandwiched between the substrate and a semiconductor wafer to be tested so that the first bump is in electrical contact with the contact of the substrate and the second bump is in electrical contact with the semiconductor wafer.

Abstract: In a fault analysis of large-scale integrated (LSI) circuits, a potential distribution image of a non-defective product and another potential distribution image of a defective product are displayed alternately and continuously in time, so that it is possible to acquire in real time an image of any location within a whole surface of the LSI chip. As a result, it can be viewed as if the potential distribution image of the non-defective product and the potential distribution image of the defective product are overlapped or superimposed with over time. Accordingly, a different portion between the non-defective and defective potential distribution images can be seen distinguishably from a coincident portion between the non-defective and defective potential distribution images, so that it is possible to trace the different portion in real time.

Abstract: The apparatus for collectively burning-in or testing a plurality of semiconductor chips disposed on a wafer without dicing the chips into individuals, the apparatus including a testing substrate, an active circuit disposed on the testing substrate for activating chips disposed on the wafer to be tested, a plurality of pads disposed on the testing substrate and positioned so that the pads are disposed in alignment with bonding pads of the chips disposed on the wafer when the testing substrate is overlaid on the wafer, and an anisotropic conductive layer disposed on the pads.

Abstract: A semiconductor integrated circuit fault analyzing apparatus includes an electron beam tester and controller. The electron beam tester includes an electron gun assembly for generating a primary electron beam and forms a voltage contrast image on the basis of a detection amount of secondary electrons obtained by irradiating the primary electron beam from the electron gun assembly onto a semiconductor integrated circuit serving as a target to be tested and supplied with a test pattern signal, thereby specifying a faulty circuit portion of the semiconductor integrated circuit using the formed voltage contrast image.

Abstract: An automatic testing apparatus includes an expert rule which is derived from expert knowledge and defines a tree of successively traceable nodes interconnected by decision branches which lead to a plurality of fault modes. Each of the nodes defines a particular test pattern and a corresponding expected value. One of the nodes is specified and a test pattern defined by the specified node is applied to an LSI chip under test and a result signal is derived therefrom. This result signal is compared with the expected value defined by the specified node to produce a comparison result. The tree of the expert rule is traced from the specified node to a subsequent node according to the comparison result and the subsequent node is specified instead of the previously specified node. The process is repeated as the tree is traced from one node to another until one of the fault modes is reached to identify a chip failure.

Abstract: An MOSIC is provided with an input and/or output protective circuit which includes a first semiconductor region formed in a semiconductor substrate with a PN junction and electrically coupled between an input or output terminal and a transistor to be protected and a second semiconductor region formed so as to surround the first region. The PN junction formed between the second region and the substrate is reverse-biased, whereby the second region absorbs carriers which are undesirably injected from the first region into the substrate in an electrical operation of the IC.

Abstract: A semiconductor device in which a logic information can be held stably without being influenced by .alpha.-rays, is disclosed. The major feature of the device resides in that a capacitor is provided at a control terminal of a transistor holding a logic information thereby to increase an effective capacitance of the control terminal.

Abstract: A high-density integrated circuit is disclosed, which comprises at least three stacked wiring layers, the lowest layer being formed of polycrystalline and including silicon gates of a plurality of insulated-gate field-effect transistors, one of the upper layers being formed of polycrystalline silicon and used for feeding a power supply to the transistors, and the other of the upper layers being formed of high-conductivity metal. Where the upper polycrystalline silicon wiring layer is under the metal wiring layer, it is preferably of a mesh-like pattern.

Abstract: A semiconductor device having a contact structure which does not lose the merit of high density circuit integration and yet can suppress generation of a leakage current is disclosed. In its basic form, the semiconductor device comprises a semiconductor substrate of one conductivity type having a first region of opposite conductivity type extending from one major surface of the semiconductor substrate to the interior of the substrate. A semiconductor layer extends on the semiconductor substrate via a first insulating film from a contact with the one major surface of the semiconductor substrate outside the first region of opposite conductivity type to a point immediately adjacent the first region. A second insulating film covers the first region of opposite conductivity type and the semiconductor layer. An aperture formed in the second insulating film exposes a portion of the first region of opposite conductivity type and a portion of the semiconductor layer close to the first region portion.

Abstract: A memory device in which an information can be easily written without failure is disclosed. The memory device comprises means for supplying a memory cells with a first voltage as a power supply thereto when a read operation is performed and means for supplying at least selected one of the memory cells with a second voltage which is smaller than the first voltage in absolute value.