Patents by Inventor Tohru Yasuda
Tohru Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8742786Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.Type: GrantFiled: March 24, 2009Date of Patent: June 3, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Kazufumi Komura, Katsumi Furukawa, Keiichi Fujimura, Takayoshi Nakamura, Tohru Yasuda, Hirohisa Nishiyama, Nobuyoshi Nakaya, Kanta Yamamoto, Shigetaka Asano
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Publication number: 20090243627Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.Type: ApplicationFiled: March 24, 2009Publication date: October 1, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kazufumi KOMURA, Katsumi Furukawa, Keiichi Fujimura, Takayoshi Nakamura, Tohru Yasuda, Hirohisa Nishiyama, Nobuyoshi Nakaya, Kanta Yamamoto, Shigetaka Asano
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Patent number: 7330043Abstract: A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.Type: GrantFiled: March 15, 2005Date of Patent: February 12, 2008Assignee: Fujitsu LimitedInventors: Seiji Yamamoto, Hirosuke Koumyoji, Tohru Yasuda, Mikio Ishikawa, Isaya Sobue, Hajime Sato, Chiaki Furukawa, Akira Sugiura, Akihiro Iwase
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Publication number: 20050156589Abstract: A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.Type: ApplicationFiled: March 15, 2005Publication date: July 21, 2005Inventors: Seiji Yamamoto, Hirosuke Koumyoji, Tohru Yasuda, Mikio Ishikawa, Isaya Sobue, Hajime Sato, Chiaki Furukawa, Akira Sugiura, Akihiro Iwase
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Patent number: 6885212Abstract: A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.Type: GrantFiled: February 3, 2003Date of Patent: April 26, 2005Assignee: Fujitsu LimitedInventors: Seiji Yamamoto, Hirosuke Koumyoji, Tohru Yasuda, Mikio Ishikawa, Isaya Sobue, Hajime Sato, Chiaki Furukawa, Akira Sugiura, Akihiro Iwase
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Publication number: 20030234661Abstract: A multi-bus semiconductor device and a method of its probing test perform the DC test for individual pads of a device while dealing with an adequate number of devices for simultaneous measurement based on the scheme of input/output pad number compressive test. The semiconductor device includes switch elements SW0-SW4 connected between input/output pads P0-P4 and a testing line L0 so that pads in an arbitrary combination, among the off-probe pads P1-P4 that are not made in contact with the tester probe Pr0, are selected for testing in correspondence to the combination of switch elements that are turned on. The input/output buffers of the pads under test are deactivated to block their internal current paths. The corresponding switch elements are turned on to connect the off-probe pads under test to the probe pad P0 that is made in contact with the tester probe Pr0, and the leak current of the probes is measured with the tester TS.Type: ApplicationFiled: February 3, 2003Publication date: December 25, 2003Applicant: Fujitsu LimitedInventors: Seiji Yamamoto, Hirosuke Koumyoji, Tohru Yasuda, Mikio Ishikawa, Isaya Sobue, Hajime Sato, Chiaki Furukawa, Akira Sugiura, Akihiro Iwase
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Patent number: 5506808Abstract: Disclosed is a data reading process as well as an improved semiconductor memory device. Input data supplied to the memory device is written in one of memory cells via a pair of bit lines when a write enable signal is active. After writing of the input data is completed, an equalizing circuit is activated to equalize the potential levels of bit lines used in data writing. An output circuit of the memory device is controlled such that the input data is forcibly output as output data from the memory device during the equalization immediately after writing of the input data is completed.Type: GrantFiled: September 14, 1994Date of Patent: April 9, 1996Assignees: Fujitsu Limited, Fujitsu VLSI LimitedInventors: Katsuyuki Yamada, Tohru Yasuda
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Patent number: 5433860Abstract: A process for treating waste washing water, which is only slightly affected by temperature, can dispense with any chemical, and wherein the quality of treated water is not affected by a change in the waste water concentration. The process comprises conducting impregnation with an impregnant having a composition comprising triethylene glycol dimethacrylate, 2-hydroxyethyl methacrylate, lauryl methacrylate, nonionic surfactant and azobisisobutyronitrile; separating the impregnant thereafter; washing the surface of the impregnated article with water; and treating the waste water by filtering the liquid having the above composition though a filter having a retained particle diameter of at most 20 .mu.m.Type: GrantFiled: January 12, 1994Date of Patent: July 18, 1995Assignee: Loctite CorporationInventor: Tohru Yasuda