Patents by Inventor TOKIHIRO YOKONO

TOKIHIRO YOKONO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240032357
    Abstract: For example, a decrease in luminance in response to a change in a viewing angle is reduced. Provided is a display device including pixel parts arranged two-dimensionally. Each of the pixel parts includes a first electrode, a second electrode provided to face the first electrode and divided into a plurality of electrode parts, and an electroluminescent layer provided between the first electrode and the second electrode.
    Type: Application
    Filed: December 17, 2021
    Publication date: January 25, 2024
    Inventor: TOKIHIRO YOKONO
  • Publication number: 20220254854
    Abstract: A display device according to the present disclosure includes: a drive circuit array substrate including drive circuits arranged in an array pattern on a semiconductor substrate; and light emitting elements arranged in an array pattern over the drive circuits and driven by the drive circuits, in which in a drive circuit group including a plurality of the drive circuits that are adjacent to each other, a well tap is provided in a part of the drive circuits of the plurality of the drive circuits included in the drive circuit group.
    Type: Application
    Filed: June 29, 2021
    Publication date: August 11, 2022
    Inventor: Tokihiro Yokono
  • Publication number: 20210287621
    Abstract: An active matrix substrate 10 configuring the display panel includes a plurality of gate lines provided in each of pixel segments Snm arrayed in a matrix form, and a plurality of data lines crossing the gate lines. The pixel segments Snm are provided respectively with gate line drive circuitry 13. Each of the gate line drive circuitry 13 is connected to drive control lines 152 and 153 that are supplied with drive control signals Sxm and Sym commanding drive or stop of the gate line drive circuitry. The gate line drive circuitry 13 having received the drive control signal commanding drive scans the gate lines in the pixel segment including the gate line drive circuitry 13.
    Type: Application
    Filed: September 22, 2017
    Publication date: September 16, 2021
    Inventors: Kohhei TANAKA, Takayuki NISHIYAMA, Ryo YONEBAYASHI, Tokihiro YOKONO
  • Patent number: 10877342
    Abstract: Provided is a display device in which variation in white balance is suppressed even if wiring lines are arranged in pixels. The display device includes: gate lines; source lines 15S; drive elements connected to the gate lines and the source lines 15S; pixel electrodes connected to the drive elements; and color filters provided corresponding to the pixel electrodes. The pixel electrodes are provided in one-to-one correspondence with subpixels, and a plurality of subpixels 18R, 18G, and 18B constitute one pixel. The display device further includes wiring lines L provided in a pixel region so as to extend along either the gate lines or the source lines. At least some of the wiring lines L are arranged in pixel aperture regions of the subpixels 18. The arrangement pitch P1 of the wiring lines L is larger than the pixel pitch (3×Sa).
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 29, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kohhei Tanaka, Ryo Yonebayashi, Keisuke Yoshida, Takayuki Nishiyama, Tokihiro Yokono
  • Patent number: 10720116
    Abstract: The invention provides a technique inhibiting luminance unevenness among pixels. An active matrix substrate has a plurality of pixel electrodes PXB each connected to a corresponding one of gate lines 13 and a corresponding one of source lines 15. The active matrix substrate includes a common electrode 14 facing each of the pixel electrodes PXB, and an auxiliary line 17 connected to the common electrode 14. The active matrix substrate further includes a plurality of drive circuits disposed in part of a display region and each configured to drive a corresponding one of the gate lines 13. The drive circuits are each connected to a control line provided for supply of a drive signal. The drive signal has first potential and second potential lower than the first potential alternately at constant cycles. The control line has a line portion 161 extending substantially in parallel with the gate lines 13.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 21, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tokihiro Yokono, Takayuki Nishiyama, Ryo Yonebayashi, Kohhei Tanaka
  • Patent number: 10679578
    Abstract: The display device includes drive circuits 301 provided in correspondence to the gate lines, respectively, and alternately switches a scanning period for scanning the gate lines and a non-scanning period during one vertical scanning period. The drive circuit 301 includes netA(n), an output switching element M5 connected to netA(n), and a reset circuit R. The output switching element M5 applies a selection voltage to the gate line GLn. The potential of netA(n) changes between a first potential that is equal to or higher than a threshold voltage of the output switching element M5, and a second potential that is lower than the first potential. In the drive circuit 301 wherein a period while netA(n) thereof has the second potential overlaps with the non-scanning period, the reset circuit R resets the potential of netA(n) to the second potential, before the resumption of the scanning period after the non-scanning period.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 9, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kohhei Tanaka, Kaoru Yamamoto, Tokihiro Yokono
  • Patent number: 10629147
    Abstract: Provided is a technique of causing less display irregularities to occur when the scanning of the gate lines is resumed in a display device in which the scanning of gate lines is performed intermittently. A display device includes a display panel, and a driving circuitry that includes a plurality of drive circuits for scanning gate lines. The driving circuitry alternately switches a scanning period in which the gate lines are scanned, and a non-scanning period in which the scanning of the gate lines is suspended, during one vertical scanning period, according to a control signal. Each driving circuit 301n includes a first switching element N that applies a selection voltage to the gate line; an internal line netA; a second switching element A that charges the internal line netA to a first potential; and a third switching element B that includes a drain electrode connected to the internal line netA, and a source electrode having a second potential that is lower than the first potential.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: April 21, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Yamamoto, Kohhei Tanaka, Tokihiro Yokono
  • Patent number: 10621938
    Abstract: A display device includes a display panel, and drive circuits sequentially scanning gate lines and supplied with any of M-phase (M: three or greater) drive signals having different phases and a first potential or a second potential (lower) at predetermined cycles. The drive circuit includes netA(n) whose potential changes by drive signal with the first/second potential as reference, and an output circuit switching a corresponding gate line to a selected/unselected state and including first output switch including a gate connected to netA(n+1) of a first drive circuit different from the drive circuit, a drain supplied with the drive signal, and a source connected to the gate line. Difference between the potential of netA(n+1) in case of switching the gate line to the unselected/selected state and the reference potential in netA(n+1) is equal to difference between the first and second potentials or greater.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: April 14, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kohhei Tanaka, Tokihiro Yokono, Kaoru Yamamoto
  • Publication number: 20200033684
    Abstract: Provided is a display device in which variation in white balance is suppressed even if wiring lines are arranged in pixels. The display device includes: gate lines; source lines 15S; drive elements connected to the gate lines and the source lines 15S; pixel electrodes connected to the drive elements; and color filters provided corresponding to the pixel electrodes. The pixel electrodes are provided in one-to-one correspondence with subpixels, and a plurality of subpixels 18R, 18G, and 18B constitute one pixel. The display device further includes wiring lines L provided in a pixel region so as to extend along either the gate lines or the source lines. At least some of the wiring lines L are arranged in pixel aperture regions of the subpixels 18. The arrangement pitch P1 of the wiring lines L is larger than the pixel pitch (3×Sa).
    Type: Application
    Filed: March 29, 2018
    Publication date: January 30, 2020
    Inventors: Kohhei TANAKA, Ryo YONEBAYASHI, Keisuke YOSHIDA, Takayuki NISHIYAMA, Tokihiro YOKONO
  • Publication number: 20200027417
    Abstract: The invention provides a technique inhibiting luminance unevenness among pixels. An active matrix substrate has a plurality of pixel electrodes PXB each connected to a corresponding one of gate lines 13 and a corresponding one of source lines 15. The active matrix substrate includes a common electrode 14 facing each of the pixel electrodes PXB, and an auxiliary line 17 connected to the common electrode 14. The active matrix substrate further includes a plurality of drive circuits disposed in part of a display region and each configured to drive a corresponding one of the gate lines 13. The drive circuits are each connected to a control line provided for supply of a drive signal. The drive signal has first potential and second potential lower than the first potential alternately at constant cycles. The control line has a line portion 161 extending substantially in parallel with the gate lines 13.
    Type: Application
    Filed: March 27, 2018
    Publication date: January 23, 2020
    Inventors: Tokihiro YOKONO, Takayuki NISHIYAMA, Ryo YONEBAYASHI, Kohhei TANAKA
  • Publication number: 20190293991
    Abstract: Provided is a normally black-type liquid crystal display panel that has high productivity. In a pixel (3) contacting a light shielding layer (5), in order for a difference to be small between an area of a light shielding part in a blue picture element (2B) which has a largest area covered with the light shielding layer (5) and an area of a light shielding part in each of a red picture element (2R) and a green picture element (2G), a picture element electrode (4) is divided in each of the red picture element (2R) and the green picture element (2G).
    Type: Application
    Filed: November 2, 2017
    Publication date: September 26, 2019
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Ryo YONEBAYASHI, Takayuki NISHIYAMA, Kohhei TANAKA, Tokihiro YOKONO
  • Publication number: 20190114984
    Abstract: A display device includes a display panel including gate lines, and drive circuits sequentially scanning the gate lines and supplied with any of M-phase (M: three or greater) drive signals having different phases and a first potential or a second potential (lower) at predetermined cycles. The drive circuit includes netA(n) whose potential changes by one drive signal with the first/second potential as reference, and an output circuit switching a corresponding gate line to a selected/unselected state and including at least one first output switch including a gate connected to netA(n+1) of a first drive circuit different from the drive circuit, a drain supplied with the drive signal, and a source connected to the gate line. Difference between the potential of netA(n+1) in case of switching the gate line to the unselected/selected state and the reference potential in netA(n+1) is equal to difference between the first and second potentials or greater.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 18, 2019
    Inventors: KOHHEI TANAKA, TOKIHIRO YOKONO, KAORU YAMAMOTO
  • Publication number: 20190096353
    Abstract: The display device includes drive circuits 301 provided in correspondence to the gate lines, respectively, and alternately switches a scanning period for scanning the gate lines and a non-scanning period during one vertical scanning period. The drive circuit 301 includes netA(n), an output switching element M5 connected to netA(n), and a reset circuit R. The output switching element M5 applies a selection voltage to the gate line GLn. The potential of netA(n) changes between a first potential that is equal to or higher than a threshold voltage of the output switching element M5, and a second potential that is lower than the first potential. In the drive circuit 301 wherein a period while netA(n) thereof has the second potential overlaps with the non-scanning period, the reset circuit R resets the potential of netA(n) to the second potential, before the resumption of the scanning period after the non-scanning period.
    Type: Application
    Filed: September 28, 2018
    Publication date: March 28, 2019
    Inventors: KOHHEI TANAKA, KAORU YAMAMOTO, TOKIHIRO YOKONO
  • Publication number: 20190080658
    Abstract: Provided is a technique of causing less display irregularities to occur when the scanning of the gate lines is resumed in a display device in which the scanning of gate lines is performed intermittently. A display device includes a display panel, and a driving circuitry that includes a plurality of drive circuits for scanning gate lines. The driving circuitry alternately switches a scanning period in which the gate lines are scanned, and a non-scanning period in which the scanning of the gate lines is suspended, during one vertical scanning period, according to a control signal. Each driving circuit 301n includes a first switching element N that applies a selection voltage to the gate line; an internal line netA; a second switching element A that charges the internal line netA to a first potential; and a third switching element B that includes a drain electrode connected to the internal line netA, and a source electrode having a second potential that is lower than the first potential.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 14, 2019
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: KAORU YAMAMOTO, KOHHEI TANAKA, TOKIHIRO YOKONO