Abstract: A pattern recognition apparatus includes a pattern preprocessing part having a plurality of outputs, and a clock oscillator, an information consolidator and a memory having a plurality of nonlinear oscillating circuits, respectively. Each of the oscillating circuits includes a plurality of inputs for controlling the oscillation condition and at least one output. In the information consolidator, the output of each oscillating circuit is interconnected to predetermined inputs of other oscillating circuits in a predetermined relation, and the inputs of the oscillating circuits are coupled to the outputs of the pattern preprocessing part in a predetermined distribution. The clock oscillator receives, as a main exciting signal, the sum of a group of signals obtained by phase-adjusting the output of a substantial part of oscillating circuits contained in the information consolidator.