Patents by Inventor Tokiyoshi Matsuda

Tokiyoshi Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10770553
    Abstract: In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer containing as a major component an ?-phase oxide semiconductor crystal; and a second semiconductor layer positioned on the first semiconductor layer and containing as a major component an oxide semiconductor crystal with a tetragonal crystal structure.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 8, 2020
    Assignee: FLOSFIA INC.
    Inventors: Tokiyoshi Matsuda, Takashi Shinohe, Shingo Yagyu, Takuto Igawa
  • Publication number: 20200279955
    Abstract: An industrially useful p-type oxide semiconductor with an enhanced semiconductor characteristic and a method of forming the p-type oxide semiconductor is provided. By using a metal oxide (for example, iridium oxide) gas as a raw material and conducting a crystal growth on a base with a corundum structure (for example, a sapphire substrate) until a film thickness to be equal to or more than 50 nm, a p-type oxide semiconductor film with a corundum structure includes a film thickness of equal to or more than 50 nm and a surface roughness of equal to or less than 10 nm is obtained.
    Type: Application
    Filed: November 15, 2018
    Publication date: September 3, 2020
    Inventors: Isao TAKAHASHI, Tokiyoshi MATSUDA, Takashi SHINOHE
  • Patent number: 10580648
    Abstract: In a first aspect of a present inventive subject matter, a semiconductor device includes a first semiconductor layer that is an electron-supply layer containing as a major component a first semiconductor crystal with a metastable crystal structure; and a second semiconductor layer that is an electron-transit layer containing as a major component a second semiconductor crystal with a hexagonal crystal structure. The first semiconductor crystal contained in the first semiconductor layer is different in composition from the second semiconductor crystal comprised in the second semiconductor layer.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: March 3, 2020
    Assignees: FLOSFIA INC., KYOTO UNIVERSITY
    Inventors: Riena Jinno, Shizuo Fujita, Kentaro Kaneko, Tokiyoshi Matsuda, Takashi Shinohe, Toshimi Hitora
  • Patent number: 10460934
    Abstract: According to an aspect of a present inventive subject matter, a crystalline film includes a crystalline metal oxide as a major component, the crystalline film includes a corundum structure, a surface area that is 9 ?m2 or more, and a dislocation density that is less than 5×106 cm?2.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 29, 2019
    Assignees: FLOSFIA INC., NATIONAL INSTITUTE FOR MATERIALS SCIENCE, KYOTO UNIVERSITY, SAGA UNIVERSITY
    Inventors: Yuichi Oshima, Shizuo Fujita, Kentaro Kaneko, Makoto Kasu, Katsuaki Kawara, Takashi Shinohe, Tokiyoshi Matsuda, Toshimi Hitora
  • Publication number: 20190103465
    Abstract: In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer containing as a major component an ?-phase oxide semiconductor crystal; and a second semiconductor layer positioned on the first semiconductor layer and containing as a major component an oxide semiconductor crystal with a tetragonal crystal structure.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 4, 2019
    Inventors: Tokiyoshi MATSUDA, Takashi SHINOHE, Shingo YAGYU, Takuto IGAWA
  • Publication number: 20190074178
    Abstract: In a first aspect of a present inventive subject matter, a semiconductor device includes a first semiconductor layer that is an electron-supply layer containing as a major component a first semiconductor crystal with a metastable crystal structure; and a second semiconductor layer that is an electron-transit layer containing as a major component a second semiconductor crystal with a hexagonal crystal structure. The first semiconductor crystal contained in the first semiconductor layer is different in composition from the second semiconductor crystal comprised in the second semiconductor layer.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 7, 2019
    Inventors: Riena JINNO, Shizuo FUJITA, Kentaro KANEKO, Tokiyoshi MATSUDA, Takashi SHINOHE, Toshimi HITORA
  • Publication number: 20190057866
    Abstract: According to an aspect of a present inventive subject matter, a crystal includes: a corundum-structured oxide semiconductor as a major component, the corundum-structured oxide semiconductor including gallium and/or indium and doped with a dopant including germanium; a principal plane; a carrier concentration that is 1×1018/cm3 or more; and an electron mobility that is 20 cm2/Vs or more.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 21, 2019
    Inventors: Yuichi OSHIMA, Shizuo FUJITA, Kentaro KANEKO, Makoto KASU, Katsuaki KAWARA, Takashi SHINOHE, Tokiyoshi MATSUDA, Toshimi HITORA
  • Publication number: 20190055646
    Abstract: According to an aspect of a present inventive subject matter, a method for producing a crystalline film includes gasifying a metal source to turn the metal source into a metal-containing raw-material gas; supplying the metal-containing raw-material gas and an oxygen-containing raw-material gas into a reaction chamber onto a substrate; and supplying a reactive gas into the reaction chamber onto the substrate to form a crystalline film under a gas flow of the reactive gas.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 21, 2019
    Inventors: Yuichi OSHIMA, Katsuaki KAWARA, Takashi SHINOHE, Tokiyoshi MATSUDA, Toshimi HITORA
  • Publication number: 20190057865
    Abstract: According to an aspect of a present inventive subject matter, a crystalline film includes a crystalline metal oxide as a major component, the crystalline film includes a corundum structure, a surface area that is 9 ?m2 or more, and a dislocation density that is less than 5×106cm?2.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 21, 2019
    Inventors: Yuichi OSHIMA, Shizuo FUJITA, Kentaro KANEKO, Makoto KASU, Katsuaki KAWARA, Takashi SHINOHE, Tokiyoshi MATSUDA, Toshimi HITORA
  • Publication number: 20190055667
    Abstract: According to an aspect of a present inventive subject matter, a method for producing a crystalline film includes; gasifying a metal source containing a metal to turn the metal source into a metal-containing raw-material gas; supplying the metal-containing raw-material gas and an oxygen-containing raw-material gas into a reaction chamber onto a substrate including a buffer layer; and supplying a reactive gas into the reaction chamber onto the substrate to form a crystalline film on the substrate under a gas flow of the reactive gas.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 21, 2019
    Inventors: Yuichi OSHIMA, Shizuo FUJITA, Kentaro KANEKO, Makoto KASU, Katsuaki KAWARA, Takashi SHINOHE, Tokiyoshi MATSUDA, Toshimi HITORA
  • Publication number: 20190006472
    Abstract: In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer including an ?-phase crystalline oxide semiconductor with a first composition, and a second semiconductor layer including an ?-phase crystalline oxide semiconductor with a second composition that is different from the first composition of the first semiconductor layer, and the second semiconductor layer is layered on the first semiconductor layer.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 3, 2019
    Inventors: Tokiyoshi MATSUDA, Takashi SHINOHE, Toshimi HITORA
  • Patent number: 7993964
    Abstract: A manufacturing method of a semiconductor device includes forming an oxide semiconductor thin film layer of zinc oxide, wherein at least a portion of the oxide semiconductor thin film layer in an as-deposited state includes lattice planes having a preferred orientation along a direction perpendicular to the substrate and a lattice spacing d002 of at least 2.619 ?.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: August 9, 2011
    Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Takashi Hirao, Takahiro Hiramatsu, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda
  • Patent number: 7981734
    Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: July 19, 2011
    Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
  • Patent number: 7977169
    Abstract: A semiconductor device includes an oxide semiconductor thin film layer primarily including zinc oxide having at least one orientation other than (002) orientation. The zinc oxide may have a mixed orientation including (002) orientation and (101) orientation. Alternatively, the zinc oxide may have a mixed orientation including (100) orientation and (101) orientation.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: July 12, 2011
    Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Takashi Hirao, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu
  • Publication number: 20090286351
    Abstract: A manufacturing method of a semiconductor device includes forming an oxide semiconductor thin film layer of zinc oxide, wherein at least a portion of the oxide semiconductor thin film layer in an as-deposited state includes lattice planes having a preferred orientation along a direction perpendicular to the substrate and a lattice spacing d002 of at least 2.619 ?.
    Type: Application
    Filed: July 27, 2009
    Publication date: November 19, 2009
    Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Takashi HIRAO, Takahiro HIRAMATSU, Mamoru FURUTA, Hiroshi FURUTA, Tokiyoshi MATSUDA
  • Publication number: 20090269881
    Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.
    Type: Application
    Filed: July 8, 2009
    Publication date: October 29, 2009
    Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Mamoru FURUTA, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
  • Patent number: 7598520
    Abstract: A semiconductor device includes an oxide semiconductor thin film layer of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate of the semiconductor device and a lattice spacing d002 of at least 2.619 ?.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: October 6, 2009
    Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Takashi Hirao, Takahiro Hiramatsu, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda
  • Patent number: 7576394
    Abstract: A thin film transistor includes a substrate, and a pair of source/drain electrodes (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: August 18, 2009
    Assignees: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Mamoru Furuta, Takashi Hirao, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu, Hiromitsu Ishii, Hitoshi Hokari, Motohiko Yoshida
  • Publication number: 20070278490
    Abstract: A semiconductor device includes an oxide semiconductor thin film layer of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate of the semiconductor device and a lattice spacing d002 of at least 2.619 ?.
    Type: Application
    Filed: June 1, 2007
    Publication date: December 6, 2007
    Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Takashi Hirao, Takahiro Hiramatsu, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda
  • Publication number: 20070187678
    Abstract: A semiconductor device includes an oxide semiconductor thin film layer primarily including zinc oxide having at least one orientation other than (002) orientation. The zinc oxide may have a mixed orientation including (002) orientation and (101) orientation. Alternatively, the zinc oxide may have a mixed orientation including (100) orientation and (101) orientation.
    Type: Application
    Filed: February 9, 2007
    Publication date: August 16, 2007
    Applicants: Kochi Industrial Promotion Center, Casio Computer Co., Ltd.
    Inventors: Takashi Hirao, Mamoru Furuta, Hiroshi Furuta, Tokiyoshi Matsuda, Takahiro Hiramatsu