Abstract: A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.

Abstract: A semiconductor memory device is provided which has a plurality of memory cells each including a pair of cross-coupled metal insulated gate field effect transistors having channels of N-conductivity type, and a pair of load resistors of polycrystalline silicon respectively coupled to the pair of cross-coupled transistors. A peripheral circuit is also provided which is constituted by metal insulated gate field effect transistors having channels of the N-conductivity type and metal insulated gate field effect transistors having channels of P-conductivity type. The semiconductor memory device is formed in an N-type semiconductor substrate, and the pair of cross-coupled metal insulated gate field effect transistors of the memory cells are formed in a well region of P-type which forms a PN-junction with the semiconductor substrate to help reduce the susceptibility to soft errors.

Abstract: Herein disclosed is a semiconductor memory device which is composed of a peripheral circuit unit equipped with a gate protection circuit having a protection resistor and a memory cell unit so that it can be used as an MISFET type static RAM and which is characterized in that the protection resistor is made of a polycrystalline silicon film having substantially the same resistivity as that of an overlying polycrystalline silicon film formed to merge into the load resistor of the memory cell unit.

Abstract: A semiconductor memory has dynamic memory cells, such as one-MOS transistor cells, a detector circuit which detects changes in applied address signals, and a timing generator circuit which receives detection outputs of the detector circuit. When the address signals are changed, various timing signals are responsively produced from the timing generator circuit. In response to the timing signals generated in succession, data lines to which the memory cells are coupled are first precharged, and one of the memory cells is selected after the precharge of the data lines. Data delivered from the selected memory cell to the data line is amplified when the operation of a sense amplifier is started. The amplified data is supplied to an external terminal through a column switch, a main amplifier, an output amplifier, etc., which are similarly operated in succession. Since the semiconductor memory of this arrangement forms a pseudo-static memory, it requires only a small number of external timing signals.

Abstract: Herein disclosed is a semiconductor memory device which is composed of a peripheral circuit unit equipped with a gate protection circuit having a protection resistor and a memory cell unit so that it can be used as an MISFET type static RAM and which is characterized in that the protection resistor is made of a polycrystalline silicon film having substantially the same resistivity as that of an overlying polycrystalline silicon film formed to merge into the load resistor of the memory cell unit.

Abstract: In a MOS static RAM, data lines disposed in a memory array and common data lines to be coupled with the data lines through a data line selection circuit are supplied with bias voltages of a level lower than a power source voltage level through bias MOSFETs. Normally, where the stand-by period of the RAM is long, the bias voltages of the data lines and the common data lines are abnormally raised by the leakage currents or tailing currents of the bias MOSFETs. As a result, the data read-out speed of the RAM is lowered. Such abnormal potential increases of the data lines and the common data lines are prevented by connecting resistance elements of comparatively high resistances (such as made of polycrystalline silicon layers), between the respective data lines and common data lines and the ground point of the circuitry.

Abstract: Digit lines, connected to the input and output terminals of a memory cell composed of MISFETs, are coupled to common data lines through a switching circuit which is controlled by a decoder circuit. There is also connected with the digit lines a load which is composed of a plurality of enhancement mode MISFETs connected in series in the diode form. The high level of the signals at the digit lines is lowered by the action of the load means. In response to the reduction in the potentials at the digit lines, the switching means is rendered conductive at an early rise time of control signals. As a result, the operating speed of the memory circuit can be increased.

Abstract: On the surface of an insulating film formed on the surface of a semiconductor substrate on which an MOS type semiconductor device to be protected is formed, there are formed a first polycrystal silicon member having input and output terminals and a resistivity lower than 1 K.OMEGA./.quadrature. and a second polycrystalline silicon member having a resistivity lower than 1 K.OMEGA./.quadrature. and being maintained at a fixed potential. This second polycrystalline silicon member faces at least a part of the first silicon member with polycrystalline silicon of a resistivity higher than 100 K.OMEGA./.quadrature. interposed therebetween. The input terminal of the first polycrystalline silicon member is connected to an input pad of the MOS type semiconductor device to be protected and the output terminal of the first polycrystalline silicon member is connected to an input gate of the semiconductor device to be protected.

Abstract: An offset gate MIS device is fabricated by forming an insulating film with a gate insulator portion as a part thereof on the surface of a semiconductor substrate having one conductivity type, providing a gate electrode on a portion of the insulating film, using the gate electrode as a mask to apply impurities of the other conductivity type with a first impurity concentration to the surface of the semiconductor substrate through the insulating film, forming a shielding film on the surface of that portion of the insulating film which is near the gate insulator portion beneath the gate electrode, using the shielding film as a mask to remove an unmasked portion of the insulating film so as to selectively expose the surface of the semiconductor substrate, applying impurities of the other conductivity type with a second impurity concentration higher than the first impurity concentration to the exposed surface of the semiconductor substrate, and heating the resultant structure to diffuse the impurities into the semi

Abstract: In a semiconductor integrated circuit having polycrystalline silicon interconnections and metal interconnections, a low resistance layer, containing impurities to a high concentration for the polycrystalline silicon interconnections, is formed in predetermined parts of an undoped polycrystalline silicon layer which is deposited on a first insulator film on a semiconductor substrate, a second insulator film is deposited on the polycrystalline silicon layer under the state under which the undoped parts are left at least around through-holes to be formed, and the metal interconnections at least parts of which run in a direction intersecting the polycrystalline silicon interconnections are provided on the second insulator film, the necessary contacts between the metal interconnections and the polycrystalline silicon interconnections being made through the through-holes provided in the second insulator film in correspondence with the intersecting parts of both the interconnections.

Abstract: In an MIS type semiconductor memory device which has at least two parasitic capacitors and which delivers, at its outputs, the state of charge accumulated in at least one of the parasitic capacitors, the respective parasitic capacitors are provided with inverter circuits. Each of the inverter circuits receives, as an input signal, the state of charge accumulated in the corresponding parasitic capacitor. When charges accumulated by precharging are to be discharged, each inverter forms a discharging path for the opposite parasitic capacitor.