Abstract: Provided is a test module comprising a specified pattern detecting section that detects a specified pattern output in response to a specified test pattern from a device under test outputting output patterns in response to test patterns; a timing detecting section that detects a timing at which the specified pattern is detected; and a phase adjusting section that adjusts phases of the output patterns to match phases of expected value patterns, which are expected from the device under test as responses to the test patterns, based on the timing detected by the timing detecting section.

Abstract: Provided is a test module that tests a device under test, comprising a pattern generating section that generates a test pattern supplied to the device under test and an expected value pattern corresponding to the test pattern, based on a pattern program; an output pattern acquiring section that acquires an output pattern output by the device under test in response to the test pattern; a comparing section that compares the output pattern output and the expected value pattern; a fail counter that counts the number of times the comparing section indicates a mismatch between the output pattern and the expected value pattern; and a control section that controls operation of the fail counter according to control instructions in the pattern program.

Abstract: Provided is a test apparatus comprising a synchronization module that operates according to a reference clock and outputs a synchronization signal with a prescribed period, and a test module that operates according to a high-frequency clock with a frequency that is n times a frequency of the reference clock. The test module includes a period emulator that emulates the synchronization signal, a phase shifter that shifts a phase of the high-frequency clock by an amount equal to a result of (i) the product of n and the emulated synchronization phase data by (ii) a period of the reference clock, and a test period generating section that generates a test period pulse signal that transitions at an edge timing of the shifted high-frequency clock and test period phase data indicating a phase difference between the test period signal and an edge timing of the test period pulse signal.

Abstract: There is provided a test module comprising a random number generator that generates a pseudo random pattern and includes a controller that generates a register selection signal based on a control instruction stored on an instruction memory, a plurality of polynomial configuration registers one of which is selected by the register selection signal, each polynomial configuration register having polynomial data stored therein, a plurality of initial value configuration registers one of which is selected by the register selection signal, each initial value configuration register having an initial value stored therein, and a random number generation shift register that loads the initial value from the selected one of the plurality of initial value configuration registers and sequentially generates the pseudo random pattern based on the polynomial data stored in the selected one of the plurality of polynomial configuration registers.

Abstract: There is provided a test module comprising a random number generator that generates a pseudo random pattern and includes a controller that generates a register selection signal based on a control instruction stored on an instruction memory, a plurality of polynomial configuration registers one of which is selected by the register selection signal, each polynomial configuration register having polynomial data stored therein, a plurality of initial value configuration registers one of which is selected by the register selection signal, each initial value configuration register having an initial value stored therein, and a random number generation shift register that loads the initial value from the selected one of the plurality of initial value configuration registers and sequentially generates the pseudo random pattern based on the polynomial data stored in the selected one of the plurality of polynomial configuration registers.

Abstract: Provided is a test apparatus comprising a synchronization module that operates according to a reference clock and outputs a synchronization signal with a prescribed period, and a test module that operates according to a high-frequency clock with a frequency that is n times a frequency of the reference clock. The test module includes a period emulator that emulates the synchronization signal, a phase shifter that shifts a phase of the high-frequency clock by an amount equal to a result of (i) the product of n and the emulated synchronization phase data by (ii) a period of the reference clock, and a test period generating section that generates a test period pulse signal that transitions at an edge timing of the shifted high-frequency clock and test period phase data indicating a phase difference between the test period signal and an edge timing of the test period pulse signal.

Abstract: Provided is a test module that tests a device under test, comprising a pattern generating section that generates a test pattern supplied to the device under test and an expected value pattern corresponding to the test pattern, based on a pattern program; an output pattern acquiring section that acquires an output pattern output by the device under test in response to the test pattern; a comparing section that compares the output pattern output and the expected value pattern; a fail counter that counts the number of times the comparing section indicates a mismatch between the output pattern and the expected value pattern; and a control section that controls operation of the fail counter according to control instructions in the pattern program.

Abstract: Provided is a test module comprising a specified pattern detecting section that detects a specified pattern output in response to a specified test pattern from a device under test outputting output patterns in response to test patterns; a timing detecting section that detects a timing at which the specified pattern is detected; and a phase adjusting section that adjusts phases of the output patterns to match phases of expected value patterns, which are expected from the device under test as responses to the test patterns, based on the timing detected by the timing detecting section.