Patents by Inventor Tokushige Hisatsugu

Tokushige Hisatsugu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070281221
    Abstract: A stencil mask (10) for use in electron beam projection exposure includes a silicon base plate (12), an insulating film (14) formed on the silicon base plate, and a silicon film (16) formed on the insulating film. In the silicon base plate and the insulating film, an opening (18) penetrating them is provided; in the silicon film, a plurality of holes (20) penetrating it and continuous to the opening are provided. In the silicon base plate and the insulating film, at least one hole (22) penetrating them is provided, and in this hole, an electrically conducting substance (24) contacting the silicon base plate and the silicon film is disposed.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 6, 2007
    Applicant: HOLON CO., LTD.
    Inventor: Tokushige Hisatsugu
  • Publication number: 20060124866
    Abstract: A method of leading an electron beam radiated from an electron emitter through openings provided in a stencil mask to a sensitive sample and exposing it includes placing the electron beam under a low field intensity where the electron beam progresses at a slow speed until reaching the openings of the stencil mask and thereafter placing the electron beam having passed through the openings of the stencil mask under a high field intensity where the electron beam progresses at a high speed. An apparatus for electron beam projection lithography comprises an electron emitter, a stencil mask having openings for permitting the electron beam radiated from the electron emitter to pass through, a base for supporting an exposure sample, and a device for placing the electron beam under a low field intensity as well as a high field generator for placing the electron beam under a high field intensity.
    Type: Application
    Filed: June 26, 2003
    Publication date: June 15, 2006
    Inventor: Tokushige Hisatsugu
  • Patent number: 6913857
    Abstract: As shown in FIG. 2, a multi-layer structured exposure mask 1 of this embodiment is provided with a frame 20 made of glass, a silicon plate 15 provided on an under surface of the frame 20, a heat absorption mask 16 provided on an under surface of the silicon plate 15, a silicon plate 11 provided on an under surface of the heat absorption mask 16 and a stencil mask 14 provided on an under surface of the silicon plate 11. The stencil mask 14 is made up of a silicon substrate and is provided with a slit-shaped patterning opening 14a to form a resist pattern. The heat absorption mask 16 is made up of a silicon substrate coated with an SiN film and is provided with slit-shaped openings 16a shaped in almost the same way as the patterning openings 14a of the stencil mask 14. The opening 16a is shaped in such a size that will not block electron beams necessary to form a resist pattern as shown in FIG. 3(a).
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: July 5, 2005
    Assignees: Matsushita Electric Industrial Co., Ltd., PD Service Corporation
    Inventors: Masaru Sasago, Masayuki Endo, Tokushige Hisatsugu
  • Publication number: 20020192573
    Abstract: As shown in FIG. 2, a multi-layer structured exposure mask 1 of this embodiment is provided with a frame 20 made of glass, a silicon plate 15 provided on an under surface of the frame 20, a heat absorption mask 16 provided on an under surface of the silicon plate 15, a silicon plate 11 provided on an under surface of the heat absorption mask 16 and a stencil mask 14 provided on an under surface of the silicon plate 11. The stencil mask 14 is made up of a silicon substrate and is provided with a slit-shaped patterning opening 14a to form a resist pattern. The heat absorption mask 16 is made up of a silicon substrate coated with an SiN film and is provided with slit-shaped openings 16a shaped in almost the same way as the patterning openings 14a of the stencil mask 14. The opening 16a is shaped in such a size that will not block electron beams necessary to form a resist pattern as shown in FIG. 3(a).
    Type: Application
    Filed: June 25, 2002
    Publication date: December 19, 2002
    Inventors: Masaru Sasago, Masayuki Endo, Tokushige Hisatsugu
  • Patent number: 4349409
    Abstract: A method and an apparatus for plasma etching semiconductor materials by providing an intermediate electrode between the electrodes in a parallel state type plasma etching apparatus, moving the intermediate electrode by a drive mechanism, and continuously changing from a condition of high input power and high self-bias voltage to a condition of low input power and low self-bias voltage while varying the distance between the intermediate electrode and the first electrode and the RF power, thereby to remove damage or deposits that may have been formed on the surface when the semiconductor material was being subjected to processing.
    Type: Grant
    Filed: May 11, 1981
    Date of Patent: September 14, 1982
    Assignee: Fujitsu Limited
    Inventors: Hikou Shibayama, Tetsuya Ogawa, Makoto Kosugi, Tokushige Hisatsugu, Koichi Kobayashi