Abstract: A parallel union control device includes: at least one memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause each of the plurality of arithmetic units included in an parallel computer including a vector register to: successively compare input elements of a pair of input sets to undergo union processing, the pair being stored in an input operand register in the vector register; select one of the input elements as an output element of an output set, based on a comparison result; and store the output element into an output operand register in the vector register; shift a pointer pointing to the input element; load the input sets into the input operand register from a memory; store the output sets into the memory from the output operand register; and determine whether union processing performed in parallel is ended.