Abstract: When the RAM (10) is not initialized, data signals captured from the data output portions (do[n]) may include undefined value, but these data signals are not transferred to an MISR through the scan path (22). Transferred to the MISR are only the data signals (DI[n]) captured by the scan path (13). Accordingly, BIST can be applied to the combinational logic circuit (40) without requiring initialization of the RAM (10) and without being affected by undefined value. Thus, BIST to the combinational logic circuit (40) can be normally achieved in a short period.

Abstract: In the first test mode with a shift-mode signal (SM) of “1” and a test-mode signal (TM) of “1”, supplying a comparison control signal (CMP) of “1” makes a test-valid condition. Then, a comparison result between input data (D) which becomes “0” to indicate a failure and an expected value data (EXP) (an output of a comparator (21)) and an AND-operation result between a serial input (SI) and a latch data (an output of a D-FF (27)) are given to the D-FF (27) through NAND gates (28 and 29), an AND gate (30) and a selector (26). With this configuration achieved is a semiconductor integrated circuit having a test circuit which allows a quick recognition of whether there is a failure or not in an internal memory circuit under test.