Patents by Inventor Tolga Memioglu
Tolga Memioglu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10317932Abstract: One embodiment provides an apparatus. The apparatus includes a dual in-line memory module (DIMM). The DIMM includes at least one memory module integrated circuit (IC); a DIMM printed circuit board (PCB); a plurality of DIMM PCB contacts; and a capacitive structure. Each DIMM PCB contact is to couple the memory module IC to a respective DIMM connector pin. The capacitive structure is to provide a mutual capacitance between a first DIMM connector signal pin and a second DIMM connector signal pin.Type: GrantFiled: July 2, 2016Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Zhichao Zhang, Xiang Li, Kemal Aygun, Zhiguo Qian, Tolga Memioglu
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Patent number: 10103054Abstract: Capacitively coupled vertical transitions are configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board.Type: GrantFiled: March 13, 2013Date of Patent: October 16, 2018Assignee: Intel CorporationInventors: Zhichao Zhang, Zhiguo Qian, Tolga Memioglu, Kemal Aygun
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Publication number: 20180007782Abstract: One embodiment provides an apparatus. The apparatus includes a dual in-line memory module (DIMM). The DIMM includes at least one memory module integrated circuit (IC); a DIMM printed circuit board (PCB); a plurality of DIMM PCB contacts; and a capacitive structure. Each DIMM PCB contact is to couple the memory module IC to a respective DIMM connector pin. The capacitive structure is to provide a mutual capacitance between a first DIMM connector signal pin and a second DIMM connector signal pin.Type: ApplicationFiled: July 2, 2016Publication date: January 4, 2018Applicant: Intel CorporationInventors: ZHICHAO ZHANG, XIANG LI, KEMAL AYGUN, ZHIGUO QIAN, TOLGA MEMIOGLU
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Patent number: 9564407Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).Type: GrantFiled: June 20, 2016Date of Patent: February 7, 2017Assignee: Intel CorporationInventors: Zhichao Zhang, Tolga Memioglu, Tao Wu, Kemal Aygun
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Publication number: 20160300803Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).Type: ApplicationFiled: June 20, 2016Publication date: October 13, 2016Inventors: Zhichao Zhang, Tolga Memioglu, Tao Wu, Kemal Aygun
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Patent number: 9391018Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).Type: GrantFiled: February 3, 2014Date of Patent: July 12, 2016Assignee: Intel CorporationInventors: Zhichao Zhang, Tolga Memioglu, Tao Wu, Kemal Aygun
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Patent number: 9105635Abstract: A metal surface feature, such as a pad, terminating a vertical transition through a substrate, such as an IC package substrate, includes one or more stubs providing high edge surface area to couple with one or more complementary stubs on an adjacent metal surface feature to provide a desired amount of mutual capacitance that may at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent pads is provided for more than two pads to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, the pads have a large pitch (e.g., 1000 ?m) suitable for interfacing to an interposer or PCB socket, while the gap between the stubs is small (e.g., 15 ?m), as limited only by the minimum spacing allowed for metal features on the opposite side of the package employed for interfacing to the IC.Type: GrantFiled: March 13, 2013Date of Patent: August 11, 2015Assignee: Intel CorporationInventors: Nevin Altunyurt, Tolga Memioglu, Kemal Aygun
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Publication number: 20140268614Abstract: Capacitively coupled vertical transitions may be configured with a desired amount of mutual capacitance to at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent vertical transitions is achieved with overlapping metal surfaces within the vertical transitions. In embodiments, one or more of the overlapping metal surfaces are vias, via pads, or metal stub features extending off a vertical transition. In embodiments, signal paths with overlapped vertical transitions are utilized to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, capacitively coupled vertical transitions are implemented in a package substrate, an interposer, or a printed circuit board.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Inventors: Zhichao ZHANG, Zhiguo Qian, Tolga Memioglu, Kemal Aygun
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Publication number: 20140264907Abstract: A metal surface feature, such as a pad, terminating a vertical transition through a substrate, such as an IC package substrate, includes one or more stubs providing high edge surface area to couple with one or more complementary stubs on an adjacent metal surface feature to provide a desired amount of mutual capacitance that may at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent pads is provided for more than two pads to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, the pads have a large pitch (e.g., 1000 ?m) suitable for interfacing to an interposer or PCB socket, while the gap between the stubs is small (e.g., 15 ?m), as limited only by the minimum spacing allowed for metal features on the opposite side of the package employed for interfacing to the IC.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Inventors: Nevin ALTUNYURT, Tolga MEMIOGLU, Kemal AYGUN
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Publication number: 20140151875Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).Type: ApplicationFiled: February 3, 2014Publication date: June 5, 2014Inventors: Zhichao ZHANG, Tolga Memioglu, Tao Wu, Kemal Aygun
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Patent number: 8643184Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).Type: GrantFiled: October 31, 2012Date of Patent: February 4, 2014Assignee: Intel CorporationInventors: Zhichao Zhang, Tolga Memioglu, Tao Wu, Kemal Aygun
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Publication number: 20080079147Abstract: In some embodiments, an embedded array capacitor with side terminals is presented. In this regard, an integrated circuit package is introduced having a plurality of micro-vias, a plurality of dielectric layers, and an array capacitor with side terminals coupled with the micro-vias and embedded in the dielectric layers. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Inventors: Michael J. Hill, Anne E. Augustine, Tolga Memioglu