Abstract: A magnetic memory device that comprises a substrate, a memory cell including a magnetic tunnel junction which comprises a free ferromagnetic layer having a reversible magnetization direction directed perpendicular to the substrate, a pinned ferromagnetic layer having a fixed magnetization direction directed perpendicular to the substrate, and an insulating tunnel barrier layer disposed between the pinned and free layers, a first electrical circuit for applying a first current to a first conductor electrically coupled to the free layer to produce a bias magnetic field along a hard axis of the free layer, a second electrical circuit for applying a second current to a second conductor electrically coupled to the pinned layer to cause a spin momentum transfer in the free layer, wherein magnitudes of the bias magnetic field and spin momentum transfer in combination exceed a threshold and thus reverse the magnetization direction of the free layer.

Abstract: One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction has a controllable electrical resistance, is disposed at an intersection region and electrically coupled to one of the first conductive lines at its first end and to one of the second conductive lines at its second end. The electrical resistance of the magnetic tunnel junction is controlled by a joint effect of a spin-polarized current running between the first and second ends and a bias magnetic field applied simultaneously to said each magnetic tunnel junction. Other embodiments are described and shown.

Abstract: A nonvolatile latch circuit that includes a logic circuitry comprising at least an input terminal, a clock terminal, an output terminal, and a nonvolatile memory element. The logic circuitry is electrically coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal. The nonvolatile memory element is electrically coupled to the output terminal at a first end and to a intermediate voltage source at a second end. A logic state of the latch circuit responds to an input signal during an active period of a clock signal. A logic state of the nonvolatile memory element is controlled by a bidirectional current running between the first and second ends. An electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source.

Abstract: A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.

Abstract: A nonvolatile multiplexer circuit comprising an electric circuitry for selecting an output signal from a plurality of input signals based on select signals, the electric circuitry comprises at least one input terminal, at least one select terminal, and at least one output terminal; a high voltage source and low voltage source electrically coupled to a first and second source terminal, respectively of the electrical circuitry; at least one nonvolatile memory element comprising two stable logic states and electrically coupled to the output terminal at its first end and to an intermediate voltage source at its second end, wherein a logic state of the nonvolatile memory element is controlled by a bidirectional electrical current running through the memory element, and wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.

Abstract: A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.

Abstract: A nonvolatile latch circuit that includes a logic circuitry comprising at least an input terminal, a clock terminal, an output terminal, and a nonvolatile memory element. The logic circuitry is electrically coupled to a high voltage source at a first source terminal and to a low voltage source at a second source terminal. The nonvolatile memory element is electrically coupled to the output terminal at a first end and to a intermediate voltage source at a second end. A logic state of the latch circuit responds to an input signal during an active period of a clock signal. A logic state of the nonvolatile memory element is controlled by a bidirectional current running between the first and second ends. An electrical potential of the intermediate voltage source is higher than that of the low voltage source but lower than that of the high voltage source.

Abstract: One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction has a controllable electrical resistance, is disposed at an intersection region and electrically coupled to one of the first conductive lines at its first end and to one of the second conductive lines at its second end. The electrical resistance of the magnetic tunnel junction is controlled by a joint effect of a spin-polarized current running between the first and second ends and a bias magnetic field applied simultaneously to said each magnetic tunnel junction. Other embodiments are described and shown.

Abstract: A magnetic memory device that comprises a substrate, a memory cell including a magnetic tunnel junction which comprises a free ferromagnetic layer having a reversible magnetization direction directed perpendicular to the substrate, a pinned ferromagnetic layer having a fixed magnetization direction directed perpendicular to the substrate, and an insulating tunnel barrier layer disposed between the pinned and free layers, a first electrical circuit for applying a first current to a first conductor electrically coupled to the free layer to produce a bias magnetic field along a hard axis of the free layer, a second electrical circuit for applying a second current to a second conductor electrically coupled to the pinned layer to cause a spin momentum transfer in the free layer, wherein magnitudes of the bias magnetic field and spin momentum transfer in combination exceed a threshold and thus reverse the magnetization direction of the free layer.

Abstract: A magnetic transistor includes a magnetic section, a thin semiconductor layer, a first metal terminal, a second metal terminal, and a third metal terminal. The thin semiconductor layer is disposed on the magnetic section. The first metal terminal is disposed on one end of the magnetic section, acting as a gate of the magnetic transistor and capable of providing a conductive channel in the thin semiconductor layer. The second metal terminal and the third metal terminal are disposed respectively on one end and the other end of the thin semiconductor layer, capable of creating a conductive region. While the magnetic transistor is turned on, a current path is formed between the second metal terminal and the third metal terminal via the thin semiconductor layer.

Abstract: A magnetic transistor circuit with the AND, NAND, NOR and OR functions has a first, a second, a third, a fourth magnetic transistor, and a routing line. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The AND, NAND, NOR and OR logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: A magnetic transistor includes a first magnetic section, a second magnetic section, a conductive section, a first metal terminal, and a second metal terminal. The conductive section is disposed between and is in direct contact with both the first and second magnetic section. The first metal terminal is disposed on one end of an opposite surface to the conductive section of the first magnetic section. The second metal terminal is disposed on one end approximately diagonal to the first metal terminal on an opposite surface to the conductive section of the second magnetic section. While the magnetic transistor structure is turned on, a current flows through the first magnetic section and the second magnetic section via the conductive section.

Abstract: A magnetic transistor circuit with the OR, NOR, NAND and AND functions has a first, a second, a third, a fourth magnetic transistor, and a routing line. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The OR, NOR, NAND and AND logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: A magnetic transistor circuit has a first and a second magnetic transistor. These two magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The EXOR logic function of the binary system can be implemented by the control of these metal devices.

Abstract: A magnetic transistor circuit representing the data ‘1’ and ‘0’ of the binary system comprises a routing line and a magnetic transistor unit. The routing line has a current going through with a first current direction or a second current direction, wherein the first current direction and the second current direction are opposite to represent the data ‘1’ and the data ‘0’ respectively. The magnetic transistor unit couples to the routing line at an output end to control the direction of the current going through the routing line.

Abstract: The method for reducing word line currents in magnetoresistive random access memory (MRAM) includes disposing the MRAM bit between a pair of word lines according to a magnetic field strength is increased when a distance between a magnetic section and its corresponding word line is decreased.

Abstract: A magnetic OR/NAND circuit has a first, a second, a third, and a fourth magnetic transistor. These four magnetic transistors that work as the ordinary transistors can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The ‘OR’ and ‘NAND’ logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: A magnetic memory has a first, a second and a third magnetic transistor. The first magnetic transistor has a first magnetic section and a second magnetic section, wherein the first magnetic section couples to a high voltage end. The second magnetic transistor has a third magnetic section and a fourth magnetic section, wherein the third magnetic section couples to a low voltage end, and the fourth magnetic section couples to the second magnetic section of the first magnetic transistor. The third magnetic transistor has a fifth magnetic section and a sixth magnetic section, wherein the fifth magnetic section couples with the second magnetic section and the fourth magnetic section together, and the sixth magnetic section couples to an input/output end.

Abstract: A magnetic AND/NOR circuit has a first, a second, a third, and a fourth magnetic transistor. These four magnetic transistors as ordinary transistors that can be turned on or turned off by the control of several metal devices respectively disposed around the magnetic transistors. The ‘AND’ and ‘NOR’ logic functions of the binary system can be implemented by the control of these metal devices.

Abstract: An upside-down MRAM comprises a sense transistor and a plurality of sense lines. A first end of the sense transistor is electrically connected to a low voltage. The sense lines are electrically connected in parallel between a high voltage and a second end of the sense transistor. Each of the sense lines has a control logic and at least one memory bit, and the memory bit is connected in series between the high voltage and the control logic.