Patents by Inventor Tom Bereiter

Tom Bereiter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6263452
    Abstract: A computer system in a fault-tolerant configuration employees multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: July 17, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Douglas E. Jewett, Tom Bereiter, Bryan Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, Krayn W. Fey, Jr., John Posdro, Kenneth C. Debacker, Nikhil A. Mehta
  • Patent number: 6073251
    Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: June 6, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Douglas E. Jewett, Tom Bereiter, Bryan Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, deceased, Krayn W. Fey, Jr., John Posdro, Kenneth C. DeBacker, Nikhil A. Mehta
  • Patent number: 5327553
    Abstract: A fault-tolerant computer system employs a pseudo-filesystem to dynamically manage the hardware components. A directory which appears as a standard, hierarchical directory in this filesystem contains a file for each component; each file maps to either a hardware component or a software module. The pseudo-filesystem hierarchy is determined during system initialization and is automatically updated whenever the software or hardware configuration changes. The pseudo-filesystem, called /config filesystem herein, is implemented as a Unix filesystem in the Unix filesystem switch. This pseudo-filesystem method may be implemented in a fault-tolerant, redundant computer system configuration having multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units.
    Type: Grant
    Filed: November 6, 1992
    Date of Patent: July 5, 1994
    Assignee: Tandem Computers Incorporated
    Inventors: Douglas E. Jewett, Tom Bereiter, Brian Vetter
  • Patent number: 5295258
    Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.
    Type: Grant
    Filed: January 5, 1990
    Date of Patent: March 15, 1994
    Assignee: Tandem Computers Incorporated
    Inventors: Douglas E. Jewett, Tom Bereiter, Brian Vetter, Randall G. Banton, Richard W. Cutts, Jr., Donald C. Westbrook, deceased, Kyran W. Fey, Jr., John Pozdro, Kenneth C. Debacker, Nikhil A. Mehta