Abstract: A power management mechanism maintains power to a processor and an integrated memory. Read-only logic and a cache are also provided. At power on, the read-only logic configures the cache as an internal memory and loads executable instructions in the cache. A copy of the executable instructions is stored in the internal memory. A branch instruction is also stored. Thereafter, the processor uses the copy of the executable instructions and present status information. The processor is programmed to issue a reset signal when a failure is detected. The read-only logic responds to the reset signal by going to the branch instruction in the internal memory, which directs the processor to use the copy of the executable instructions and status information in the internal memory circuit. The operating state is restored and the processor is instructed to execute the next instruction in the copy of executable instructions.

Abstract: A power management mechanism maintains power to a processor and an integrated memory. Read-only logic and a cache are also provided. At power on, the read-only logic configures the cache as an internal memory and loads executable instructions in the cache. A copy of the executable instructions is stored in the internal memory. A branch instruction is also stored. Thereafter, the processor uses the copy of the executable instructions and present status information. The processor is programmed to issue a reset signal when a failure is detected. The read-only logic responds to the reset signal by going to the branch instruction in the internal memory, which directs the processor to use the copy of the executable instructions and status information in the internal memory circuit. The operating state is restored and the processor is instructed to execute the next instruction in the copy of executable instructions.