Abstract: An high performance Fast Fourier Transform implementation in hardware is achieved through placement of a number of Butterfly/Dragonfly or “FLY” cells that run concurrently during a transformation process. The bank of FLY cells interacts according to FFT/IFFT algorithms through use of a resource-sharing fabric. The resource-sharing fabric allows the bank of cells to accept raw input, exchange intermediate results according to the FLY network topology, apply phase factors at appropriate junctures, and finally generate output, which may then be digit-reversed according to particular FFT/IFFT algorithmic variant chosen, e.g. “Division In Time” or “Division In Frequency”.