Patents by Inventor Tom Daenen

Tom Daenen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of determining current-voltage characteristics of a device
    Patent number: 7181352
    Abstract: A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: February 20, 2007
    Assignee: Interuniversitaire Microelektronica Centrum (IMEC) vzw
    Inventors: Natarajan Mahadeva Iyer, Steven Thijs, Vesselin K. Vassilev, Tom Daenen, Vincent De Heyn
  • Method of determining current-voltage characteristics of a device
    Publication number: 20040239346
    Abstract: A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline.
    Type: Application
    Filed: April 2, 2004
    Publication date: December 2, 2004
    Inventors: Natarajan Mahadeva Iyer, Steven Thijs, Vesselin K. Vassilev, Tom Daenen, Vincent De Heyn