Abstract: Methods and apparatus for providing delivery of content to client devices of a network via both multicast and unicast mechanisms. In one embodiment, a system for use in a managed content delivery network is described to bridge multicast to unicast, so that the total network bandwidth consumption is significantly lower than a corresponding unicast-only delivery solution, yet which still provides improved quality of service and user viewing experience as compared to a multicast-only delivery solution. In addition, various exemplary aspects of the present disclosure are readily adapted for real-time multicast to unicast streaming of audio and data to, among other things, minimize network bandwidth usage, while maintaining the guaranteed delivery of unicast streams with little or no modification to the existing client device logic.

Abstract: A test set includes at least one signal input port, a test circuitry, a processor, a user-input device, and a display. The test circuitry couples to and receives signals from the at least one signal input port. The test circuitry then generates test data corresponding to the received signals. The processor couples to and receives test data from the test circuitry and generates test results. The processor also couples to and receives commands from the user-input device. The processor further operatively couples to the graphical display that receives and displays the test results from the processor. In one embodiment, the test set is capable of performing line qualification and connectivity testing. A modem module can be used to facilitate connectivity testing. The modem module can be a plug-in module with a common interface to the test set. The modem module can also contain a fingerprint value that identifies the module type and the software revision number to the test set.

Abstract: A test set includes at least one signal input port, a test circuitry, a processor, a user-input device, and a display. The test circuitry couples to and receives signals from the at least one signal input port. The test circuitry then generates test data corresponding to the received signals. The processor couples to and receives test data from the test circuitry and generates test results. The processor also couples to and receives commands from the user-input device. The processor further operatively couples to the graphical display that receives and displays the test results from the processor. In one embodiment, the test set is capable of performing line qualification and connectivity testing. A modem module can be used to facilitate connectivity testing. The modem module can be a plug-in module with a common interface to the test set. The modem module can also contain a fingerprint value that identifies the module type and the software revision number to the test set.

Abstract: A test set includes at least one signal input port, a test circuitry, a processor, a user-input device, and a display. The test circuitry couples to and receives signals from the at least one signal input port. The test circuitry then generates test data corresponding to the received signals. The processor couples to and receives test data from the test circuitry and generates test results. The processor also couples to and receives commands from the user-input device. The processor further operatively couples to the graphical display that receives and displays the test results from the processor. In one embodiment, the test set is capable of performing line qualification and connectivity testing. A modem module can be used to facilitate connectivity testing. The modem module can be a plug-in module with a common interface to the test set. The modem module can also contain a fingerprint value that identifies the module type and the software revision number to the test set.

Abstract: A test set includes at least one signal input port, a test circuitry, a processor, a user-input device, and a display. The test circuitry couples to and receives signals from the at least one signal input port. The test circuitry then generates test data corresponding to the received signals. The processor couples to and receives test data from the test circuitry and generates test results. The processor also couples to and receives commands from the user-input device. The processor further operatively couples to the graphical display that receives and displays the test results from the processor. In one embodiment, the test set is capable of performing line qualification and connectivity testing. A modem module can be used to facilitate connectivity testing. The modem module can be a plug-in module with a common interface to the test set. The modem module can also contain a fingerprint value that identifies the module type and the software revision number to the test set.

Abstract: A test set includes at least one signal input port, a test circuitry, a processor, a user-input device, and a display. The test circuitry couples to and receives signals from the at least one signal input port. The test circuitry then generates test data corresponding to the received signals. The processor couples to and receives test data from the test circuitry and generates test results. The processor also couples to and receives commands from the user-input device. The processor further operatively couples to the graphical display that receives and displays the test results from the processor. In one embodiment, the test set is capable of performing line qualification and connectivity testing. A modem module can be used to facilitate connectivity testing. The modem module can be a plug-in module with a common interface to the test set. The modem module can also contain a fingerprint value that identifies the module type and the software revision number to the test set.

Abstract: A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved.

Abstract: A stacked ROM device utilizes the same conductivity type for the ROM cells in both the top and the bottom ROM cell matrixes. The stacked ROM device comprises a first ROM cell matrix which comprises conductively doped source and drain lines having a first conductivity type in a semiconductor substrate having a second conductivity type. For example, the source and drain lines are implemented with n-type doping in a p-type substrate. A second ROM cell matrix comprises conductively doped source and drain lines having the first conductivity type in a semiconductor layer which overlies and is isolated from the semiconductor substrate. A plurality of shared wordlines is disposed between the first and second ROM cell matrixes. A plurality of bit lines is isolated from and overlies the semiconductor layer.

Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, power supply pins and ground pins are provided on opposite edges of a package with input address pins being arranged therebetween and output data pins being arranged outside the same. Control pins and a nonconnected excess pin are arranged in the center. This allows the package to omit wires and reduce chip size.

Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.

Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.

Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.

Abstract: A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved.

Abstract: An integrated circuit comprises a functional module such as a FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port is provided on the integrated circuit coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array.

Abstract: A floating gate memory with a protocol which terminates a program load cycle upon detecting a predetermined address and/or data pattern, providing positive indication of the end of the load cycle, and eliminating the requirement for a long pulse in a controlled signal. Command logic executes a process to store a block of data in response to a sequence of addresses and data segments received at the input/output circuitry, and detects the last segment in a block of data in response to a pattern including at least one of the addresses and data segments received at the input/output circuitry. One pattern includes consecutive matching addresses. Pattern match logic included in the command logic is coupled to the input/output circuitry and stores addresses in the sequence and compares them with a next address to indicate a matching address. Alternatively, the pattern includes both matching addresses and data segments with corresponding comparator circuitry.

Abstract: A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.

Abstract: In order to reduce the chip size of a semiconductor device as well as to separate noises between at least two types of pads having different functions, at least one Vcc and at least one Vss are provided on opposite edges of a package (101) so that output pins or I/O pins are arranged therebetween and input pins are arranged outside the same. Non-connected excess pins (NC) are arranged on upper and lower boundaries, for omitting wires and reducing the chip size.

Abstract: An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is-coupled through a top block select transistor to global bitline.

Abstract: A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address. If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder to prevent access to the defective sectors while maintaining sequential addressing remaining sectors in the array. The step of partitioning includes configuring the sector decoder to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the N address bits in common with the defective sector when m is between 1 and N-1.

Abstract: Wordline driver circuitry drives a plurality of wordlines in a flash EEPROM memory array in a first mode which selects between a positive voltage and ground, and a second mode which selects between a negative voltage and ground. A first supply voltage selector supplies positive voltage during the first mode, and a second mode reference voltage, such as ground, in the second mode. A second supply voltage selector supplies the first mode reference voltage such as ground in the first mode, and the negative voltage during a second mode. An inverting driver has an input which receives a wordline select signal, and an output coupled to the wordline, a first supply voltage input connected to the first supply voltage selector, and second supply voltage input connected to the second supply voltage selector.