Abstract: In one embodiment, a method includes measuring a rate of traffic received at a leaf node, marking a plurality of packets in the flow as protected at the leaf node to match the rate of traffic with a configured rate of traffic for the flow at the leaf node, and dropping a plurality of non-protected packets at the leaf node when a queue at the leaf node is congested. A minimum bandwidth is provided for the flow based on the configured rate of traffic at the leaf node. The leaf node comprises an ingress node or an egress node connected to a fabric. An apparatus is also disclosed herein.

Abstract: In one embodiment, a method includes measuring a rate of traffic received at a leaf node, marking a plurality of packets in the flow as protected at the leaf node to match the rate of traffic with a configured rate of traffic for the flow at the leaf node, and dropping a plurality of non-protected packets at the leaf node when a queue at the leaf node is congested. A minimum bandwidth is provided for the flow based on the configured rate of traffic at the leaf node. The leaf node comprises an ingress node or an egress node connected to a fabric. An apparatus is also disclosed herein.

Abstract: A switching bus architecture enables efficient transfer of data within a network switch having a plurality of ports interconnected by a high-performance switching bus. The architecture is preferably implemented as novel port interface and forwarding engine circuitry that cooperate to efficiently transmit data to, and receive data from, the switching bus in accordance with a 2-tier arbitration policy that ensures adequate port access to the bus. As a result of such a cooperating arrangement, the architecture improves the transfer efficiency of the switch by providing all ports sufficient bus access to convey accurate data throughout the switch.

Abstract: A color blocking logic (CBL) mechanism implements spanning tree states with respect to data frames transported between port interface circuitry over a link connecting different switches in a network. Each port interface circuit preferably supports multiple virtual local area network (VLAN) designations and associates those VLAN designations with data frames transmitted to and from the switch over the link. The CBL mechanism cooperates with a forwarding engine of the switch to selectively enable the port interface circuit to receive certain VLAN-designated frames, and to discard others, in an efficient and cost-effective manner.

Abstract: An encapsulation mechanism efficiently transports packets between ports of different switches in a network on the basis of, inter alia, virtual local area network (VLAN) associations among those ports. The switches are preferably interconnected by a novel interswitch link (ISL) mechanism that appends ISL destination and source information, along with ISL error detection information, to VLAN-modified packets. The ISL mechanism keeps the VLAN associations of the packets intact during transfer between the switches in accordance with a high-performance switching bus architecture.

Abstract: An address translation mechanism quickly and efficiently renders forwarding decisions for data flames transported among ports of a high-performance switch on the basis of, inter alia, virtual local area network (VLAN) associations among the ports. The translation mechanism comprises a plurality of forwarding tables, each of which contains entries having unique index values that translate to selection signals for ports destined to received the data frames. Each port is associated with a unique index value and a VLAN identifier to facilitate multicast data transfers within the switch at accelerated speeds and addressing capabilities.