Abstract: A CCD shift register involves a serial input channel and a serial output channel interconnected by a plurality of parallel channels formed in a semiconductor body with separate arrays of multi electrode sets of phase electrodes overlying the input, parallel and output channels. A summing gate electrode common to all of the parallel channels is adjacent the output channel. Control means actuates the gate to transfer charge packets from each parallel channel into the output channel and clocks the charge packets to the output. Two such shift registers are provided with means to inject time samples of an input signal alternately to the two shift registers and to multiplex the outputs therefrom.

Abstract: A charge coupled device analog multiplexer in which a CCD shift register is characterized by an array of sets of phase electrodes. A plurality of charge packet injection input channels lead to an electrode in each of preselected sets in the array. A transfer gate common to all input channels admits charge packets to the array. A clock applies shift voltages to the array to move said charge packets to the multiplexer output where detector means responds to charge packets appearing at the output.