Patents by Inventor Tom Graettinger
Tom Graettinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140159136Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.Type: ApplicationFiled: February 3, 2014Publication date: June 12, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Ron Weimer, Kyu Min, Tom Graettinger, Nirmal Ramaswamy
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Patent number: 8643082Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.Type: GrantFiled: October 19, 2011Date of Patent: February 4, 2014Assignee: Micron Technology, Inc.Inventors: Ron Weimer, Kyu Min, Tom Graettinger, Nirmal Ramaswamy
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Publication number: 20120032252Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.Type: ApplicationFiled: October 19, 2011Publication date: February 9, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Ron Weimer, Kyu Min, Tom Graettinger, Nirmal Ramaswamy
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Patent number: 8058140Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.Type: GrantFiled: April 9, 2010Date of Patent: November 15, 2011Assignee: Micron Technology, Inc.Inventors: Ron Weimer, Kyu Min, Tom Graettinger, Nirmal Ramaswamy
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Publication number: 20100197131Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.Type: ApplicationFiled: April 9, 2010Publication date: August 5, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Ron Weimer, Kyu Min, Tom Graettinger, Nirmal Ramaswamy
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Patent number: 7705389Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.Type: GrantFiled: August 29, 2007Date of Patent: April 27, 2010Assignee: Micron Technology, Inc.Inventors: Ron Weimer, Kyu Min, Tom Graettinger, Nirmal Ramaswamy
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Publication number: 20090057744Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.Type: ApplicationFiled: August 29, 2007Publication date: March 5, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Ron Weimer, Kyu Min, Tom Graettinger, Nirmal Ramaswamy
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Patent number: 6940112Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.Type: GrantFiled: August 30, 2002Date of Patent: September 6, 2005Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Mark Visokay, Tom Graettinger, Dan Gealy, Gurtej Sandhu, Cem Basceri, Steve Cummings
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Patent number: 6869877Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.Type: GrantFiled: August 30, 2002Date of Patent: March 22, 2005Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Mark Visokay, Tom Graettinger, Dan Gealy, Gurtej Sandhu, Cem Basceri, Steve Cummings
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Publication number: 20030025142Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.Type: ApplicationFiled: August 30, 2002Publication date: February 6, 2003Applicant: Micron Technology, Inc.Inventors: Howard E. Rhodes, Mark Visokay, Tom Graettinger, Dan Gealy, Gurtej Sandhu, Cem Basceri, Steve Cummings
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Publication number: 20030003621Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.Type: ApplicationFiled: August 30, 2002Publication date: January 2, 2003Applicant: Micron Technology, Inc.Inventors: Howard E. Rhodes, Mark Visokay, Tom Graettinger, Dan Gealy, Gurtej Sandhu, Cem Basceri, Steve Cummings
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Patent number: 6492241Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.Type: GrantFiled: April 10, 2000Date of Patent: December 10, 2002Assignee: Micron Technology, Inc.Inventors: Howard E. Rhodes, Mark Visokay, Tom Graettinger, Dan Gealy, Gurtej Sandhu, Cem Basceri, Steve Cummings