Patents by Inventor Tom Grebs

Tom Grebs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10121716
    Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: November 6, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Tom Grebs, Simon John Molloy
  • Patent number: 10062624
    Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: August 28, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Tom Grebs, Simon John Molloy
  • Publication number: 20170301595
    Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 19, 2017
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Tom Grebs, Simon John Molloy
  • Publication number: 20170301596
    Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 19, 2017
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Tom Grebs, Simon John Molloy
  • Patent number: 9721860
    Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: August 1, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Tom Grebs, Simon John Molloy
  • Publication number: 20160133534
    Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 12, 2016
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Tom Grebs, Simon John Molloy