Patents by Inventor Tom Gregorich

Tom Gregorich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6891275
    Abstract: An area array package comprising a die attach area for attaching a die to a substrate, a network of staggered bond fingers, and a network of bond islands for coupling bond wires between the bond islands and die bond pads is provided. A network of package leads, for example, a network of solder balls in a ball grid array, is depopulated to permit greater trace route flexibility and via placement within the substrate. Stacked die and multi-chip packages are also disclosed. A method for accommodating a high pin-count die in an area array package is also included.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: May 10, 2005
    Assignee: Qualcomm Incorporated
    Inventors: Ryan Lane, Edward Reyes, Mark Veatch, Tom Gregorich
  • Publication number: 20040195703
    Abstract: An area array package comprising a die attach area for attaching a die to a substrate, a network of staggered bond fingers, and a network of bond islands for coupling bond wires between the bond islands and die bond pads is provided. A network of package leads, for example, a network of solder balls in a ball grid array, is depopulated to permit greater trace route flexibility and via placement within the substrate. Stacked die and multi-chip packages are also disclosed. A method for accommodating a high pin-count die in an area array package is also included.
    Type: Application
    Filed: April 21, 2004
    Publication date: October 7, 2004
    Inventors: Ryan Lane, Edward Reyes, Mark Veatch, Tom Gregorich
  • Patent number: 6762495
    Abstract: An area area package includes a plurality of solder balls not used as electrical connectors. These non-connected solder balls, or “dummy balls,” provide protection to solder balls connected to live pins and therefore increase reliability of the area array package. The dummy balls may be placed in the corners, along the diagonals or in other high stress location on the area array package. To further increase reliability, a continuous copper ball land pad may be used to connect each group of corner dummy balls. Continuous copper pads help to reduce stress on the dummy balls. For center-depopulated BGA packages, an array of dummy balls may be used in the center of the package to prevent substrate bending and improve drop test reliability.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: July 13, 2004
    Assignee: Qualcomm Incorporated
    Inventors: Edward Reyes, Ryan Lane, Tiona Marburger, Tom Gregorich
  • Publication number: 20040075178
    Abstract: An area array package comprising a die attach area for attaching a die to a substrate, a network of staggered bond fingers, and a network of bond islands for coupling bond wires between the bond islands and die bond pads is provided. A network of package leads, for example, a network of solder balls in a ball grid array, is depopulated to permit greater trace route flexibility and via placement within the substrate. Stacked die and multi-chip packages are also disclosed. A method for accommodating a high pin-count die in an area array package is also included.
    Type: Application
    Filed: July 21, 2003
    Publication date: April 22, 2004
    Inventors: Ryan Lane, Edward Reyes, Mark Veatch, Tom Gregorich