Abstract: A split-steer amplifier with an invertible phase output, includes a first transistor having its base coupled to a positive node of an input port, its emitter coupled to ground, and collector connected to a positive intermediate node; a second transistor having its base coupled to a negative node of the input port, its emitter coupled to ground, and collector connected to a negative intermediate node; and multiple output ports each having a transistor arrangement operable to couple a positive node of that output port to the positive intermediate node and a negative node of that output port to the negative intermediate node, operable to couple the positive node of that output port to the negative intermediate node and the negative node of that output port to the positive intermediate node, and operable to decouple the positive node and the negative node of that output port from the intermediate nodes.

Abstract: Illustrative methods and circuits to verify operation of phase shifters. One illustrative method includes: obtaining a first set of in-phase and quadrature components (I1,Q1) of a phase shifter output signal with a first setting; measuring a second set of components (I2,Q2) with a second setting, the second setting being offset from the first by a predetermined phase difference; and combining the first and second sets to determine whether their relationship corresponds to the predetermined phase difference. An illustrative transmitter includes: a phase shifter, an I/Q mixer, and a processing circuit. The phase shifter converts a transmit signal into an output signal having a programmable phase shift. The I/Q mixer mixes the output signal with a reference signal to obtain in-phase and quadrature components of the output signal. The processing circuit is coupled to the I/Q mixer implement the disclosed method.

Abstract: A MIMO amplifier circuit operable to couple one or more selectable input ports to one or more selectable output ports. The circuit includes N input transistors and M output transistors. Each input transistor has its base coupled to a respective input port node, its emitter coupled to ground, and its collector connected to an intermediate node. Each output transistor has its base coupled to a bias node, its emitter connected to the intermediate node, and its collector coupled to a respective output port nodes. Each input transistor enables the respective input port node when its base is biased. Each output transistor enables the respective output port node when its bias node is asserted. The base of the input transistor for each enabled port is biased to provide a quiescent current I0*m/n through that input transistor, where m is the number of enabled output ports and n is the number of enabled input ports.

Abstract: A MIMO amplifier circuit operable to couple one or more selectable input ports to one or more selectable output ports. The circuit includes N input transistors and M output transistors. Each input transistor has its base coupled to a respective input port node, its emitter coupled to ground, and its collector connected to an intermediate node. Each output transistor has its base coupled to a bias node, its emitter connected to the intermediate node, and its collector coupled to a respective output port nodes. Each input transistor enables the respective input port node when its base is biased. Each output transistor enables the respective output port node when its bias node is asserted. The base of the input transistor for each enabled port is biased to provide a quiescent current I0*m/n through that input transistor, where m is the number of enabled output ports and n is the number of enabled input ports.

Abstract: An improved circuit configuration is disclosed for calibrating and/or verifying the operation of phase shifters in a phased array radar system. In one illustrative embodiment, a method includes: (i) programming a set of phase shifters to convert a radio frequency signal into a set of channel signals; (ii) splitting off a monitor signal from each channel signal while coupling the set of channel signals to a set of antenna feeds; and (iii) while taking the monitor signals in pairs associated with adjacent channels, measuring a relative phase between each pair of monitor signals.

Abstract: An array of one or more integrated circuits includes at least one local input port to receive a chirp signal from a local generator; one or more primary input ports to each receive a respective chirp signal from a remote source; a primary switch arrangement operable to switch between the chirp signals from the at least one local input port and the one or more primary input ports to produce a composite signal having a chirp sequence with at least one chirp that begins during a settling period of a previous chirp; and one or more primary output ports to supply a local oscillator signal to a transmitter and a receiver based on the composite signal. The roles of master circuit and follower circuit can change during operation of the array.

Abstract: A radiation pattern of a phased array antenna, comprising a plurality of antenna elements, may be dynamically modified using phase shifters to apply variable phase shifts between antenna elements. In a phased array antenna designed for airborne applications, the phase shifters may be required to enable a fine phase-shifting resolution and to operate over a wide temperature range. The phase shifters may also be required to perform while exhibiting small process variations, small form factor, low power consumption, and low loss. One possible solution to this is a passive vector-interpolating phase shifter configured to exhibit such characteristics.

Abstract: Automotive radar methods and systems for enhancing resistance to interference using a built-in self-test (BIST) module. In one illustrative embodiment, an automotive radar transceiver includes: a signal generator that generates a transmit signal; a modulator that derives a modulated signal from the transmit signal using at least one of phase and amplitude modulation; at least one receiver that mixes the transmit signal with a receive signal to produce a down-converted signal, the receive signal including the modulated signal during a built-in self-test (BIST) mode of operation; and at least one transmitter that drives a radar antenna with a selectable one of the transmit signal and the modulated signal.

Abstract: A multi-antenna signal encoding method comprises receiving an antenna signal and a reference signal a first mixer; producing, using the first mixer, a down-converted signal based on the antenna signal and the reference signal; receiving, at one or more second mixers, second antenna signals and second reference signals orthogonal to the first reference signal; producing one or more second down-converted signals based on the one or more second antenna signals and the one or more second reference signals; converting, using an analog-to-digital converter, a summation signal corresponding to a sum of the first down-converted signal and the one or more second down-converted signals, into a digital receive-signal; and extracting, at a processor, a plurality of digital signals from the digital receive-signal, wherein each of the plurality of digital signals corresponds to one of the first antenna signal and the one or more second antenna signals.

Abstract: A MIMO amplifier circuit operable to couple one or more selectable input ports to one or more selectable output ports. The circuit includes N input transistors and M output transistors. Each input transistor has its base coupled to a respective input port node, its emitter coupled to ground, and its collector connected to an intermediate node. Each output transistor has its base coupled to a bias node, its emitter connected to the intermediate node, and its collector coupled to a respective output port nodes. Each input transistor enables the respective input port node when its base is biased. Each output transistor enables the respective output port node when its bias node is asserted. The base of the input transistor for each enabled port is biased to provide a quiescent current I0*m/n through that input transistor, where m is the number of enabled output ports and n is the number of enabled input ports.

Abstract: A radiation pattern of a phased array antenna, comprising a plurality of antenna elements, may be dynamically modified using phase shifters to apply variable phase shifts between antenna elements. In a phased array antenna designed for airborne applications, the phase shifters may be required to enable a fine phase-shifting resolution and to operate over a wide temperature range. The phase shifters may also be required to perform while exhibiting small process variations, small form factor, low power consumption, and low loss. One possible solution to this is a passive vector-interpolating phase shifter configured to exhibit such characteristics.

Abstract: Disclosed active reflector apparatus and methods that inhibit self-induced oscillation. One illustrative apparatus embodiment includes an amplifier and an adjustable phase shifter. The amplifier amplifies a receive signal to generate a transmit signal, the transmit signal causing interference with the receive signal. The adjustable phase shifter modifies the phase of the transmit signal relative to that of the receive signal to inhibit oscillation. A controller may periodically test a range of settings for the adjustable phase shifter to identify undesirable phase shifts prone to self-induced oscillation, and may maintain the phase shift setting at a value that inhibits oscillation.

Abstract: An illustrative digital latch includes: a differential transistor pair (“track pair”) capacitively coupled to a differential input signal to cause a differential output voltage between output nodes to track the differential input signal when a clock signal is asserted; a cross-coupled transistor pair (“latch pair”) coupled to the output nodes to latch the differential output voltage when the clock signal is de-asserted; a differential transistor pair (“clock pair”) that steers a bias current between the track pair and the latch pair; and a matched set of bias transistors that determines the bias current for the clock pair and a reference voltage on a reference voltage node, the reference voltage node being coupled to a base of each transistor in the track pair by equal bias resistances.

Abstract: A radiation pattern of a phased array antenna, comprising a plurality of antenna elements, may be dynamically modified using phase shifters to apply variable phase shifts between antenna elements. In a phased array antenna designed for airborne applications, the phase shifters may be required to enable a fine phase-shifting resolution and to operate over a wide temperature range. The phase shifters may also be required to perform while exhibiting small process variations, small form factor, low power consumption, and low loss. One possible solution to this is a passive vector-interpolating phase shifter configured to exhibit such characteristics.