Patents by Inventor Tom Heynemann

Tom Heynemann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080065799
    Abstract: A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.
    Type: Application
    Filed: November 9, 2007
    Publication date: March 13, 2008
    Inventors: Tom Heynemann, Jeffrey Sprouse, Michael Knowles
  • Publication number: 20070078940
    Abstract: Various embodiments of systems and methods for remotely configuring network memory are disclosed. One method embodiment, among others, comprises identifying a first device as having authority to control a memory device from a remote location, and writing start-up or reset parameters to memory of the memory device from the remote location, wherein the start-up or reset parameters are used to enable remote control of the memory device corresponding to remote direct memory access (RDMA) operations.
    Type: Application
    Filed: October 5, 2005
    Publication date: April 5, 2007
    Inventors: Samuel Fineberg, Pankaj Mehra, Rahul Nim, Tom Heynemann
  • Publication number: 20050223178
    Abstract: In a system including multiple-slice processors and memories, a synchronization unit with race avoidance capability includes a delegated write engine that receives data and memory address information from the processors and writes data to the memory as a delegate for the processors.
    Type: Application
    Filed: November 16, 2004
    Publication date: October 6, 2005
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: David Garcia, Michael Knowles, Tom Heynemann, Jeffrey Sprouse