Patents by Inventor Tom Ho Wing Yu

Tom Ho Wing Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11798845
    Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: October 24, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xi Cen, Kai Wu, Min Heon, Wei Min Chan, Tom Ho Wing Yu, Peiqi Wang, Ju Ik Kang, Feihu Wang, Nobuyuki Sasaki, Chunming Zhou
  • Patent number: 11637107
    Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: April 25, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
  • Publication number: 20230115130
    Abstract: Embodiments of the present disclosure generally relate to methods for forming or otherwise producing metal silicides on a silicon surface of substrate. Exemplary metal silicides can be or include titanium silicide, cobalt silicide, nickel silicide, molybdenum silicide, or alloys thereof. In one or more embodiments, a method of forming a metal silicide is provided and includes removing a native oxide from a substrate to reveal a silicon surface of the substrate during a cleaning process, depositing a metallic layer on the silicon surface during a deposition process, and heating the substrate contained within a process region containing hydrogen gas during a silicidation process to produce a metal silicide layer on the substrate from the metallic layer and the silicon surface.
    Type: Application
    Filed: October 13, 2021
    Publication date: April 13, 2023
    Inventors: Tom Ho Wing YU, Nobuyuki SASAKI
  • Patent number: 11626410
    Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: April 11, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
  • Publication number: 20220406788
    Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
  • Publication number: 20220406790
    Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.
    Type: Application
    Filed: July 11, 2022
    Publication date: December 22, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Jianxin Lei, Wenting Hou, Rongjun Wang, Tza-Jing Gung
  • Publication number: 20220336274
    Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Inventors: Xi CEN, Kai WU, Min HEON, Wei Min CHAN, Tom Ho Wing YU, Peiqi WANG, Ju Ik KANG, Feihu WANG, Nobuyuki SASAKI, Chunming ZHOU
  • Publication number: 20220130724
    Abstract: Method for forming tungsten gap fill on a structure, including high aspect ratio structures includes depositing a tungsten liner in the structure using a physical vapor deposition (PVD) process with high ionization and an ambient gas of argon or krypton. The PVD process is performed at a temperature of approximately 20 degrees Celsius to approximately 300 degrees Celsius. The method further includes treating the structure with a nitridation process and depositing bulk fill tungsten into the structure using a chemical vapor deposition (CVD) process to form a seam suppressed boron free tungsten fill. The CVD process is performed at a temperature of approximately 300 degrees Celsius to approximately 500 degrees Celsius and at a pressure of approximately 5 Torr to approximately 300 Torr.
    Type: Application
    Filed: October 28, 2020
    Publication date: April 28, 2022
    Inventors: Xi CEN, Kai WU, Min HEON, Wei Min CHAN, Tom Ho Wing YU, Peiqi WANG, Ju Ik KANG, Feihu WANG, Nobuyuki SASAKI, Chunming ZHOU
  • Publication number: 20210327717
    Abstract: Methods and apparatus for the formation of cobalt disilicide are described. Some embodiments of the disclosure provide in-situ methods of forming cobalt disilicide. The resulting films are smoother and have lower resistance and resistivity than films formed by similar ex-situ methods. Some embodiments of the disclosure provide apparatus for performing the described methods without an air break between processes.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 21, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Tom Ho Wing Yu, Nobuyuki Sasaki, Kazuya Daito
  • Patent number: 10811257
    Abstract: A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 20, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Tzu-Yu Liu, Kyu-Ha Shim, Tom Ho Wing Yu, Zhong Qiang Hua, Adolph Miller Allen, Viabhav Soni, Ravi Rajagopalan, Nobuyuki Sasaki
  • Publication number: 20190304783
    Abstract: A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 3, 2019
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Tzu-Yu Liu, Kyu-HA Shim, Tom Ho Wing Yu, Zhong Qiang Hua, Adolph Miller Allen, Viabhav Soni, Ravi Rajagopalan, Nobuyuki Sasaki