Abstract: A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.

Abstract: A display controller within a display device includes a serial peripheral interface (SPI) that coordinates the updating of current settings for groups of light-emitting diodes (LEDs). The SPI controller operates in synchrony with a liquid-crystal display (LCD) vertical scan position in order to update the current settings for rows of LEDs in parallel with the updating of nearby rows of LCD pixels. When updating a row of LEDs, the SPI controller executes one or more SPI transactions included in an SPI program to write current settings for multiple LEDs nearly simultaneously. A compiler generates the SPI program based on the topology of LEDs included in the display device.

Abstract: In various examples, defective cells from a first layer of a multi-layer liquid crystal display (LCD) may be compensated for by using one or more cells from a second layer of the multi-layer LCD. Color values corresponding to additional cells of the first layer that may be affected by the compensation of the second layer may also be adjusted to counter the compensation in order to generate a final pixel or sub-pixel value that closely mirrors the desired value from the image data. In addition, backlighting of the LCD may be adjusted such that one or more cells of the backlights—e.g., individual light-emitting diodes (LEDs)—may be adjusted to further aid in compensating for or mitigating the appearance of the defective cell.

Abstract: In various examples, defective cells from a first layer of a multi-layer liquid crystal display (LCD) may be compensated for by using one or more cells from a second layer of the multi-layer LCD. Color values corresponding to additional cells of the first layer that may be affected by the compensation of the second layer may also be adjusted to counter the compensation in order to generate a final pixel or sub-pixel value that closely mirrors the desired value from the image data. In addition, backlighting of the LCD may be adjusted such that one or more cells of the backlights—e.g., individual light-emitting diodes (LEDs)—may be adjusted to further aid in compensating for or mitigating the appearance of the defective cell.

Abstract: A display device for measuring the end-to-end latency of a computing system. The computing system includes an input device, a computing device, and the display device. The display device is directly connected with the input device and receives input data packets generated by the input device in response to received user input events. The display device passes the input packets to the computing device for graphics processing. The display device measures the end-to-end latency comprising the sum of three latencies. A first latency comprises an input delay of the input device. A second latency comprises an amount of time between generation of the input packet and a corresponding change in pixel values caused by the input event at the display device. A third latency comprises a display latency. The display device also displays latency information associated with the measured end-to-end latency.

Abstract: A display controller progressively updates LEDs and LCD pixels in scanline order as portions of an image are scanned into a frame buffer. The display controller analyzes a first portion of the image that includes a first pixel value associated with a first LCD pixel. The display controller identifies a first LED that contributes luminance to the first LCD pixel and determines an LED current setting for the LED based on the first pixel value. The display controller then identifies a second LCD pixel that resides above the first LED and is associated with a second pixel value. The display controller configures the second LCD pixel based on the second pixel value and luminance contributions received at the second LCD pixel. Accordingly, the display controller need not wait for the entire image to be scanned into the frame buffer before initiating display of the image.

Abstract: In various examples, images rendered by a processor—such as a graphics processing unit (GPU)—may be scanned out of memory in a middle-out scan order. Various architectures for liquid crystal displays (LCDs) may be implemented to support middle-out scanning, such as dual-panel architectures, ping-pong architectures, and architectures that support both top-down scan order and middle-out scan order. As a result, display latency within the system may be reduced, thereby increasing performance of the system—especially for high-performance applications such as gaming.

Abstract: In various examples, images rendered by a processor—such as a graphics processing unit (GPU)—may be scanned out of memory in a middle-out scan order. Various architectures for liquid crystal displays (LCDs) may be implemented to support middle-out scanning, such as dual-panel architectures, ping-pong architectures, and architectures that support both top-down scan order and middle-out scan order. As a result, display latency within the system may be reduced, thereby increasing performance of the system—especially for high-performance applications such as gaming.

Abstract: A display controller within a display device includes a serial peripheral interface (SPI) that coordinates the updating of current settings for groups of light-emitting diodes (LEDs). The SPI controller operates in synchrony with a liquid-crystal display (LCD) vertical scan position in order to update the current settings for rows of LEDs in parallel with the updating of nearby rows of LCD pixels. When updating a row of LEDs, the SPI controller executes one or more SPI transactions included in an SPI program to write current settings for multiple LEDs nearly simultaneously. A compiler generates the SPI program based on the topology of LEDs included in the display device.

Abstract: A display controller within a display device includes a serial peripheral interface (SPI) that coordinates the updating of current settings for groups of light-emitting diodes (LEDs). The SPI controller operates in synchrony with a liquid-crystal display (LCD) vertical scan position in order to update the current settings for rows of LEDs in parallel with the updating of nearby rows of LCD pixels. When updating a row of LEDs, the SPI controller executes one or more SPI transactions included in an SPI program to write current settings for multiple LEDs nearly simultaneously. A compiler generates the SPI program based on the topology of LEDs included in the display device.

Abstract: A display controller progressively updates LEDs and LCD pixels in scanline order as portions of an image are scanned into a frame buffer. The display controller analyzes a first portion of the image that includes a first pixel value associated with a first LCD pixel. The display controller identifies a first LED that contributes luminance to the first LCD pixel and determines an LED current setting for the LED based on the first pixel value. The display controller then identifies a second LCD pixel that resides above the first LED and is associated with a second pixel value. The display controller configures the second LCD pixel based on the second pixel value and luminance contributions received at the second LCD pixel. Accordingly, the display controller need not wait for the entire image to be scanned into the frame buffer before initiating display of the image.

Abstract: A display controller within a display device includes a serial peripheral interface (SPI) that coordinates the updating of current settings for groups of light-emitting diodes (LEDs). The SPI controller operates in synchrony with a liquid-crystal display (LCD) vertical scan position in order to update the current settings for rows of LEDs in parallel with the updating of nearby rows of LCD pixels. When updating a row of LEDs, the SPI controller executes one or more SPI transactions included in an SPI program to write current settings for multiple LEDs nearly simultaneously. A compiler generates the SPI program based on the topology of LEDs included in the display device.

Abstract: A modulated clock device is provided that includes an update device for updating a phase of the modulated clock device. In one example, the update device includes an update phase multiplexer coupled to an output phase multiplexer of an output clock generator and configured to receive an input clock signal and one or more phases of the input clock signal; an output phase fractional counter coupled to the update phase multiplexer and configured to receive an update clock signal and to generate an output phase; and an update phase device coupled to the output phase fractional counter and to the update phase multiplexer. The output phase fractional counter is further configured to send the output phase to the output phase multiplexer and to the update phase device. The update phase device is configured to generate an update phase and to send the update phase to the update phase multiplexer.

Abstract: One embodiment of the present invention sets forth a technique for reducing motion blur in a liquid crystal display (LCD) by pulsing each frame with a relatively short pulse of backlight illumination while driving pixels within the LCD with compensated intensity values to account for LCD settling time and vertical position. An LCD drive compensation unit implements the disclosed technique to generate an intensity value for each pixel that is scanned into the LCD. The technique advantageously reduces motion blur while preserving uniform vertical display accuracy.

Abstract: One embodiment of the present invention sets forth a technique for reducing motion blur in a liquid crystal display (LCD) by pulsing each frame with a relatively short pulse of backlight illumination while driving pixels within the LCD with compensated intensity values to account for LCD settling time and vertical position. An LCD drive compensation unit implements the disclosed technique to generate an intensity value for each pixel that is scanned into the LCD. The technique advantageously reduces motion blur while preserving uniform vertical display accuracy.

Abstract: A modulated clock device is provided that includes an update device for updating a phase of the modulated clock device. In one example, the update device includes an update phase multiplexer coupled to an output phase multiplexer of an output clock generator and configured to receive an input clock signal and one or more phases of the input clock signal; an output phase fractional counter coupled to the update phase multiplexer and configured to receive an update clock signal and to generate an output phase; and an update phase device coupled to the output phase fractional counter and to the update phase multiplexer. The output phase fractional counter is further configured to send the output phase to the output phase multiplexer and to the update phase device. The update phase device is configured to generate an update phase and to send the update phase to the update phase multiplexer.

Abstract: An approach is provided for modulating an input clock signal of a clock source. In one example, a modulated clock device receives the input clock signal from the clock source, applies a sequence of digital delay devices to the input clock signal to generate one or more delayed phases of the input clock signal, sends the input clock signal and the one or more delayed phases of the input clock signal to an output phase multiplexer, selects an appropriate phase of the input clock signal from among the input clock signal and the one or more delayed phases of the input clock signal, and generates an output clock signal based on the appropriate phase of the input clock signal.