Patents by Inventor Tom Kamp
Tom Kamp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10714354Abstract: Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.Type: GrantFiled: March 1, 2017Date of Patent: July 14, 2020Assignee: Lam Research CorporationInventors: Tom Kamp, Neema Rastgar, Michael Carl Drymon
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Patent number: 10431426Abstract: A gas plenum arrangement for a substrate processing system includes a gas plenum body arranged to define a gas plenum between a coil and a processing chamber. The coil is arranged outside of an outer edge of the gas plenum body. A plurality of flux attenuating portions is arranged outside of the outer edge of the gas plenum body. The flux attenuation portions overlap the coil.Type: GrantFiled: October 12, 2016Date of Patent: October 1, 2019Assignee: LAM RESEARCH CORPORATIONInventors: Tom Kamp, Arthur H. Sato, Alex Paterson
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Publication number: 20190189447Abstract: A method for in-situ patterning a stack having a patterned mask with mask features including sidewalls and tops is provided. A plurality of patterning cycles is provided in a plasma chamber wherein each patterning cycle comprises: at least one (1) cycle of depositing an atomic layer deposition (ALD) over the mask features to create an ALD layer, wherein the ALD layer includes sidewalls over the sidewalls of the mask features and top portions over the tops of the mask features, and selectively etching the top portions of the ALD layer with respect to the sidewalls of the ALD layer.Type: ApplicationFiled: December 19, 2017Publication date: June 20, 2019Inventors: Tom KAMP, Yoko YAMAGUCHI
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Publication number: 20170178917Abstract: Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.Type: ApplicationFiled: March 1, 2017Publication date: June 22, 2017Applicant: Lam Research CorporationInventors: Tom Kamp, Neema Rastgar, Michael Carl Drymon
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Patent number: 9620376Abstract: Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.Type: GrantFiled: August 19, 2015Date of Patent: April 11, 2017Assignee: LAM RESEARCH CORPORATIONInventors: Tom Kamp, Neema Rastgar, Michael Carl Drymon
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Publication number: 20170053808Abstract: Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.Type: ApplicationFiled: August 19, 2015Publication date: February 23, 2017Inventors: Tom Kamp, Neema Rastgar, Michael Carl Drymon
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Publication number: 20170032931Abstract: A gas plenum arrangement for a substrate processing system includes a gas plenum body arranged to define a gas plenum between a coil and a processing chamber. The coil is arranged outside of an outer edge of the gas plenum body. A plurality of flux attenuating portions is arranged outside of the outer edge of the gas plenum body. The flux attenuation portions overlap the coil.Type: ApplicationFiled: October 12, 2016Publication date: February 2, 2017Inventors: Tom KAMP, Arthur H. SATO, Alex PATERSON
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Patent number: 9484214Abstract: A substrate processing system includes a processing chamber including a dielectric window and a pedestal for supporting a substrate during processing. A gas supply system supplies gas to the processing chamber. A coil is arranged outside of the processing chamber adjacent to the dielectric window. A radio frequency (RF) source supplies RF signals to the coil to create RF plasma in the processing chamber. N flux attenuating portions are arranged in a spaced pattern adjacent the coil, wherein N is an integer greater than one.Type: GrantFiled: June 2, 2014Date of Patent: November 1, 2016Assignee: LAM RESEARCH CORPORATIONInventors: Tom Kamp, Arthur Sato, Alex Paterson
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Patent number: 9396961Abstract: The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.Type: GrantFiled: February 2, 2015Date of Patent: July 19, 2016Assignee: Lam Research CorporationInventors: Reza Arghavani, Shashank C. Deshmukh, Eric A. Hudson, Tom Kamp, Samantha Tan, Gerardo Adrian Delgadino
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Publication number: 20160181117Abstract: The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations. The first etching operation partially etches the features and may take place in a reactor configured to produce a capacitively coupled plasma. The first etching operation may end before the underlying semiconductor material experiences substantial damage due to penetration of ions through the dielectric atop the semiconductor material. The second etching operation may take place in a reactor configured to produce an inductively coupled plasma. Both the first and second etching operations may themselves be multi-step, cyclic processes.Type: ApplicationFiled: February 2, 2015Publication date: June 23, 2016Inventors: Reza Arghavani, Shashank C. Deshmukh, Eric A. Hudson, Tom Kamp, Samantha Tan, Gerardo Adrian Delgadino
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Publication number: 20150235808Abstract: A substrate processing system includes a processing chamber including a dielectric window and a pedestal for supporting a substrate during processing. A gas supply system supplies gas to the processing chamber. A coil is arranged outside of the processing chamber adjacent to the dielectric window. A radio frequency (RF) source supplies RF signals to the coil to create RF plasma in the processing chamber. N flux attenuating portions are arranged in a spaced pattern adjacent the coil, wherein N is an integer greater than one.Type: ApplicationFiled: June 2, 2014Publication date: August 20, 2015Applicant: Lam Research CorporationInventors: Tom Kamp, Arthur Sato, Alex Paterson
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Patent number: 9012243Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer.Type: GrantFiled: August 27, 2014Date of Patent: April 21, 2015Assignee: Lam Research CorporationInventors: Yoshie Kimura, Tom Kamp, Eric Pape, Rohit DeshPande, Keith Gaff, Gowri Kamarthy
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Publication number: 20150053347Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system. The controller also receives critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data of the at least one previously processed wafers and the critical device parameters of the current wafer.Type: ApplicationFiled: August 27, 2014Publication date: February 26, 2015Inventors: Yoshie Kimura, Tom Kamp, Eric Pape, Rohit DeshPande, Keith Gaff, Gowri Kamarthy
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Patent number: 8901004Abstract: A method of producing plurality of etched features in an electronic device is disclosed that avoids micro-loading problems thus maintaining more uniform sidewall profiles and more uniform critical dimensions. The method comprises performing a first time-divisional plasma etch process step within a plasma chamber to a first depth of the plurality of etched features, and performing a flash process step to remove any polymers from exposed surfaces of the plurality of etched features without requiring an oxidation step. The flash process step is performed independently of the time-divisional plasma etch step. A second time-divisional plasma etch process step is performed within the plasma chamber to a second depth of the plurality of etched features. The method may be repeated until a desired etch depth is reached.Type: GrantFiled: July 20, 2010Date of Patent: December 2, 2014Assignee: Lam Research CorporationInventors: Tom Kamp, Qian Fu, I. C. Jang, Linda Braly, Shenjian Liu
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Patent number: 8852964Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.Type: GrantFiled: February 4, 2013Date of Patent: October 7, 2014Assignee: Lam Research CorporationInventors: Yoshie Kimura, Tom Kamp, Eric Pape, Rohit DeshPande, Keith Gaff, Gowri Kamarthy
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Publication number: 20140220709Abstract: Exemplary embodiments are directed to controlling CD uniformity of a wafer by controlling trim time on temperature in a plasma processing system. The plasma processing system has a wafer support assembly including a plurality of independently controllable temperature control zones across a chuck and a controller that controls each temperature control zone. The controller receives process control and temperature data associated with at least one wafer previously processed in a plasma chamber of the plasma processing system, and critical device parameters of a current wafer to be processed in the plasma chamber. The controller calculates a target trim time and a target temperature profile of the current wafer based on the process control and temperature data, and the critical device parameters. The current wafer is trimmed during the target trim time while the temperature of each device die location is controlled based on the target temperature profile.Type: ApplicationFiled: February 4, 2013Publication date: August 7, 2014Applicant: LAM RESEARCH CORPORATIONInventors: Yoshie Kimura, Tom Kamp, Eric Pape, Rohit DeshPande, Keith Gaff, Gowri Kamarthy
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Publication number: 20110021029Abstract: A method of producing plurality of etched features in an electronic device is disclosed that avoids micro-loading problems thus maintaining more uniform sidewall profiles and more uniform critical dimensions. The method comprises performing a first time-divisional plasma etch process step within a plasma chamber to a first depth of the plurality of etched features, and performing a flash process step to remove any polymers from exposed surfaces of the plurality of etched features without requiring an oxidation step. The flash process step is performed independently of the time-divisional plasma etch step. A second time-divisional plasma etch process step is performed within the plasma chamber to a second depth of the plurality of etched features. The method may be repeated until a desired etch depth is reached.Type: ApplicationFiled: July 20, 2010Publication date: January 27, 2011Applicant: Lam Research CorporationInventors: Tom Kamp, Qian Fu, I.C. Jang, Linda Braly, Shenjian Liu