Patents by Inventor Tom Kazmierski

Tom Kazmierski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flip-flop
    Patent number: 10505523
    Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: December 10, 2019
    Assignees: ARM Limited, University of Southampton
    Inventors: Anand Savanth, James Edward Myers, Yunpeng Cai, Alexander Stewart Weddell, Tom Kazmierski
  • Flip-Flop
    Publication number: 20180278244
    Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.
    Type: Application
    Filed: May 25, 2018
    Publication date: September 27, 2018
    Inventors: Anand Savanth, James Edward Myers, Yunpeng Cai, Alexander Stewart Weddell, Tom Kazmierski
  • Flip-flop
    Patent number: 9985613
    Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: May 29, 2018
    Assignees: ARM Limited, University of Southampton
    Inventors: Anand Savanth, James Edward Myers, Yunpeng Cai, Alexander Stewart Weddell, Tom Kazmierski
  • Flip-Flop
    Publication number: 20180123571
    Abstract: A single-phase flip-flop comprising: a master latch comprising: a first circuit to generate a master latch signal in response to a first master logic operation on a flip flop input signal and a first clock signal, and a second circuit to generate a master output signal in response to a second master logic operation on the first clock signal and master latch signal; a slave latch comprising: a third circuit to generate a slave output signal in response to a first slave logic operation on the first clock signal and one of the master output signal and an inverted slave output signal; and wherein the master latch is configured to capture the flip-flop input signal during a first portion of the first clock signal and the slave latch is configured to capture the master output signal during a second portion of the first clock signal.
    Type: Application
    Filed: October 27, 2016
    Publication date: May 3, 2018
    Inventors: Anand Savanth, James Edward Myers, Yunpeng Cai, Alexander Stewart Weddell, Tom Kazmierski